An associative processor architecture for air traffic control

  • H. N. Boyd
Session 10: Parallel Processor Architectures For Air Traffic Control
Part of the Lecture Notes in Computer Science book series (LNCS, volume 24)


Hardware architecture is described for an associative processor (AP) designed to augment an existing automated air traffic control system (ATC). Basically, this AP is tailored to the ATC environment from the general purpose associative processor, STARAN(a). The ACT/AP consists of two identical AP modules to be integrated into an existing ATC system with minimal impact other than to increase the system's capabilities. System availability is a primary consideration in the ATC/AP architecture and in the method of integration into the remainder of the system. The hardware of the ATC/AP is described with particular emphasis on the differences from the more general AP — STARAN — and the method of interfacing to acquire high availability.


Processing Element Memory Module Program Control Logic Shared Memory System Read Only Memory 


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  1. [1]
    E. E. Eddey and W. C. Meilander, Application of an Associative Processor to Aircraft Tracking, GER-16128, Goodyear Aerospace Corporation (20 August 1974).Google Scholar
  2. [2]
    K. E. Batcher, STARAN/RADCAP Hardware Architecture, GER-15947, Goodyear Aerospace Corporation, 22 August 1973. Paper published in Proceedings of the 1973 Sagamore Computer Conference on Parallel Processing. Syracuse University in cooperation with IEEE and ACM, Syracuse, New York, 22–24 August 1973, pp. 147–154.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1975

Authors and Affiliations

  • H. N. Boyd
    • 1
  1. 1.Goodyear Aerospace CorporationAkron

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