An associative processor architecture for air traffic control
Hardware architecture is described for an associative processor (AP) designed to augment an existing automated air traffic control system (ATC). Basically, this AP is tailored to the ATC environment from the general purpose associative processor, STARAN(a). The ACT/AP consists of two identical AP modules to be integrated into an existing ATC system with minimal impact other than to increase the system's capabilities. System availability is a primary consideration in the ATC/AP architecture and in the method of integration into the remainder of the system. The hardware of the ATC/AP is described with particular emphasis on the differences from the more general AP — STARAN — and the method of interfacing to acquire high availability.
KeywordsProcessing Element Memory Module Program Control Logic Shared Memory System Read Only Memory
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