Architectural considerations in interfacing a parallel processor to the air traffic control system
Interfacing of parallel processors and other special purpose computers to a general purpose host is a very important consideration in effectively using these processors. This paper describes how a parallel processor configuration is connected to a host machine, in this case an ARTS III(a) multiprocessor system. The constraints leading to the configuration are first presented. Then we give descriptions of the matched hardware and software interfaces which ensure that the full capabilities of the processors can be utilized and that the cost and risk of developing the system is minimized. This paper presents only one experience in designing a parallel processor to host computer interface, but some of the considerations encountered in this experience will be applicable to other such interface attempts.
KeywordsControl Unit Processing Element Radar Data Central Memory Parallel Processor
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