A reconfigurable parallel arithmetic unit

  • C. P. Hsu
  • Tse-Yun Feng
Session 9: System Architecture And Component Design
Part of the Lecture Notes in Computer Science book series (LNCS, volume 24)


  1. [1]
    J. C. Hoffmann, B. Lacaze, P. Csillag, "Multiplieur Parallels or Circuits Logiques Iteratiffs", Electronic Letters, vol. 4, No. 9, pp. 178, April 1968.Google Scholar
  2. [2]
    T. Feng, "Data Manipulating Functions in Parallel Processors and Their Implementation", IEEE Transactions on Computers, vol. C-23, No. 3, pp. 309–318, March 1974.Google Scholar
  3. [3]
    T. Feng, C. P. Hsu, "Design and Analysis of A Parallel Arithmetic Unit", Technical Report, TR-73-13, Dept. of Electrical and Computer Engineering, Syracuse University, (December 1973).Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1975

Authors and Affiliations

  • C. P. Hsu
    • 1
  • Tse-Yun Feng
    • 1
  1. 1.Department of Electrical and Computer EngineeringSyracuse UniversitySyracuse

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