On programmable parallel data routing networks via cross-bar switches for multiple element computer architectures

Abstract

This paper deals with the reduction of the number of cross-bar switches required to form a programmable data routing network [PDRN] for interconnecting multiple computing elements [CE]'s and the programming of such networks. The reduction is done by using triangular PDRN's [TPDRN's] to form a multistage network, conditioned on an a priori knowledge of interconnections. The programmability of the proposed PDRN's is specified by the design and the implementation of a route finding algorithm in a multistage PDRN. It is also found that all existing methods used for finding maximum flow in transport networks or used for finding completely matched sets [CMS] in bipartite graphs can be used to solve the middle block assignment problem in a PDRN. A set-up algorithm for a particular type of memory cell in a TPDRN is developed. The worst case propagation delays in the proposed PDRN's are also analyzed. Note that the proposed PDRN's become more advantageous when the number of CE's is large (more than 100). The applications of the proposed PDRN's may include multiprocessors, single and multiple access memory modules, dynamic allocations of memories, dynamic digital computers, digital differential analyzers, automatic patching of analog/hybrid computers with some modifications etc.