On programmable parallel data routing networks via cross-bar switches for multiple element computer architectures

  • C. J. Chen
  • A. A. Frank
Session 9: System Architecture And Component Design
Part of the Lecture Notes in Computer Science book series (LNCS, volume 24)


This paper deals with the reduction of the number of cross-bar switches required to form a programmable data routing network [PDRN] for interconnecting multiple computing elements [CE]'s and the programming of such networks. The reduction is done by using triangular PDRN's [TPDRN's] to form a multistage network, conditioned on an a priori knowledge of interconnections. The programmability of the proposed PDRN's is specified by the design and the implementation of a route finding algorithm in a multistage PDRN. It is also found that all existing methods used for finding maximum flow in transport networks or used for finding completely matched sets [CMS] in bipartite graphs can be used to solve the middle block assignment problem in a PDRN. A set-up algorithm for a particular type of memory cell in a TPDRN is developed. The worst case propagation delays in the proposed PDRN's are also analyzed. Note that the proposed PDRN's become more advantageous when the number of CE's is large (more than 100). The applications of the proposed PDRN's may include multiprocessors, single and multiple access memory modules, dynamic allocations of memories, dynamic digital computers, digital differential analyzers, automatic patching of analog/hybrid computers with some modifications etc.


Bipartite Graph Memory Cell Transport Network Connection Matrix Binary Digit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. [1]
    Hu, T. C., Integer Programming and Network Flows, Addison-Wesley Publishing Company, Menlo Park, California, 1969.Google Scholar
  2. [2]
    Liu, C. L., Introduction to Combinational Mathematics, McGraw-Hill Book Company, New York, 1968.Google Scholar
  3. [3]
    Benes, V. E., Mathematical Theory of Connecting Networks and Telephone Traffic, Academic Press, New York, 1965.Google Scholar
  4. [4]
    Hannauer, G., "Automatic Patching for Analog and Hybrid Computers," Simulation, 12, May 1969.Google Scholar
  5. [5]
    Kautz, W. H., et al., "A Cellular Interconnection Array," IEEE Trans. Compt., vol. C-17, No. 5, May 1968.Google Scholar
  6. [6]
    Thornton, J. E., "Parallel Operation in the Control Data 6600," Proc. Spring Joint Computer Conference, 1964.Google Scholar
  7. [7]
    Larson, A. L., "Theory and Design of Precision Digital Integrators Using Linear Multistep Integration Methods," Ph.D. dissertation, University of Wisconsin, Madison, 1973.Google Scholar
  8. [8]
    Barnes, G. H., et. al., "The ILLIAC IV Computer," IEEE Trans. Compt., vol. C-17, August 1968.Google Scholar
  9. [9]
    Bell, G. C. and Newell, A., Computer Structures: Readings and Examples, McGraw-Hill, New York, 1971.Google Scholar
  10. [10]
    Clos, C., "A Study of Non-blocking Switching Networks," BSTJ, No. 32, March 1953.Google Scholar
  11. [11]
    Higgins, W. H., "A Survey of Bell System Progress in Electronic Switching," BSTJ, No. 6, July–August 1965.Google Scholar
  12. [12]
    Chen, C. J., "Design of Programmable Data Routing Networks for a Dynamic Digital Computer," Ph.D. dissertation, University of Wisconsin, Madison, 1974.Google Scholar
  13. [13]
    T. Y. Feng, "Data Manipulating Functions in Parallel Processors and Their Implementations," IEEE Trans. Compt., vol. C-23, No. 3, March 1974.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1975

Authors and Affiliations

  • C. J. Chen
    • 1
  • A. A. Frank
    • 2
  1. 1.Norand CorporationCedar Rapids
  2. 2.University of WisconsinMadison

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