Parallel processing by virtual instruction
An architecture involving at least one master CPU and many auxiliary processors is proposed to restore the balance between processor and store systems in multi-programming systems.
The outline of the processor/store connections is given and the mode of operation is discussed. Parallelism is achieved by either parallel processing one task or running many tasks in parallel.
It is shown that the system will run current high level programs making its own decisions as to whether it is feasible to subtask a portion of the program. If anything is subtasked it is treated as a virtual instruction to run on its own processor. This virtual instruction is mapped onto the auxiliary processors by an associative memory.
KeywordsMain Memory Random Access Memory Virtual Instruction Physical Processor Backing Store
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