Advertisement

Parallel processing by virtual instruction

  • Cecil Kaplinsky
Session 9: System Architecture And Component Design
Part of the Lecture Notes in Computer Science book series (LNCS, volume 24)

Abstract

An architecture involving at least one master CPU and many auxiliary processors is proposed to restore the balance between processor and store systems in multi-programming systems.

The outline of the processor/store connections is given and the mode of operation is discussed. Parallelism is achieved by either parallel processing one task or running many tasks in parallel.

It is shown that the system will run current high level programs making its own decisions as to whether it is feasible to subtask a portion of the program. If anything is subtasked it is treated as a virtual instruction to run on its own processor. This virtual instruction is mapped onto the auxiliary processors by an associative memory.

Keywords

Main Memory Random Access Memory Virtual Instruction Physical Processor Backing Store 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    C. V. Ramamoorthy and M. J. Gonzalez, "A Survey of Techniques for Recognizing Parallel Processable Streams in Computer Programs," in 1969 Fall Joint Comput. Conf., AFIPS Conf. Proc., vol. 35, Montvale, N.J.: AFIPS Press 1969, pp. 1–7.Google Scholar
  2. [2]
    R. Turn, "Computers in the 1980's — Trends in Hardware Technology," Information Processing 74, North Holland, Amsterdam, 1974, pp. 137–140.Google Scholar
  3. [3]
    C. H. Kaplinsky, "The Universal Peripheral Controller — an intelligent buffered channel" Proceedings of the European Computing Conference, Online, 1974, pp. 659–670.Google Scholar
  4. [4]
    W. Walkenshaw and A. J. Oxley (Ed), Computing and Automation Division Quarterly Report, 31 December 73–31 March 74, Computing and Automation Div., Rutherford Laboratory, RL-74-072 C78.Google Scholar
  5. [5]
    M. J. Gonzalez and C. V. Ramamoorthy, "Parallel Task Execution in a Decentralized System," IEEE Trans. Comput. C.21, December 1972, pp. 1310–1322.Google Scholar
  6. [6]
    A. J. Bernstein, "Analysis of Program for Parallel Processing," IEEE Trans. Electron. Comput. vol. EC-15, October 1966, pp. 757–763.Google Scholar
  7. [7]
    W. H. Burkhart, "Automation of Program Speed-up on Parallel-Processor Computers," Computing 3, 1968, pp. 297–310.Google Scholar
  8. [8]
    C. V. Ramamoorthy, J. H. Park and H. F. Li, "Compilation Techniques for Recognition of Parallel Processable Tasks in Arithmetic Expressions," IEEE Trans. Comput., C-22, November 1973, pp. 986–997.Google Scholar
  9. [9]
    D. Knuth, "An Empirical Study of FORTRAN Programs," Software — Practice and Experience, vol. 1, 1971, pp. 105–133.Google Scholar
  10. [10]
    K. Kennedy, "A Global Flow Analysis Algorithm," International Journal of Computer Math., vol. 3, December 1971, pp. 5–15.Google Scholar
  11. [11]
    F. E. Allen, "Interprocedural Data Flow Analysis," Information Processing 74, vol. 2, North Holland 1974, pp. 398–402.Google Scholar
  12. [12]
    M. E. Conway, "Design of a Seperable Transition-Diagram Compiler," Com of ACM, vol. 6, July 1963, pp. 396–408.Google Scholar
  13. [13]
    J. E. Juliussen and F. J. Mowle, "Multiple Micro processors with Common Main and Control Memories," IEEE Trans. Comput., C-22, November 1973, pp. 999–1007.Google Scholar
  14. [14]
    P. S. Roberts and C. S. Wallace, "A Micro programmed Lexical Processor," Information Processing 71, North Holland 1972, pp. 577–581.Google Scholar
  15. [15]
    J. R. Spirn and P. J. Denning, "Experiments with Program Locality," Proc. AFIPS Conf. Fall Joint Computer Conference, 1972, pp. 611–621.Google Scholar
  16. [16]
    I. Masuda, H. Shiota, K. Noguchi and T. Ohki, "Optimization of Program Organization by Cluster Analysis," Information Process 74, North Holland 1974, pp. 261–265.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1975

Authors and Affiliations

  • Cecil Kaplinsky
    • 1
  1. 1.Computer Unit Westfield CollegeUniversity of LondonLondonEngland

Personalised recommendations