Parallel processing by virtual instruction

  • Cecil Kaplinsky
Session 9: System Architecture And Component Design
Part of the Lecture Notes in Computer Science book series (LNCS, volume 24)


An architecture involving at least one master CPU and many auxiliary processors is proposed to restore the balance between processor and store systems in multi-programming systems.

The outline of the processor/store connections is given and the mode of operation is discussed. Parallelism is achieved by either parallel processing one task or running many tasks in parallel.

It is shown that the system will run current high level programs making its own decisions as to whether it is feasible to subtask a portion of the program. If anything is subtasked it is treated as a virtual instruction to run on its own processor. This virtual instruction is mapped onto the auxiliary processors by an associative memory.


Main Memory Random Access Memory Virtual Instruction Physical Processor Backing Store 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1975

Authors and Affiliations

  • Cecil Kaplinsky
    • 1
  1. 1.Computer Unit Westfield CollegeUniversity of LondonLondonEngland

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