A control structure for parallel processing

  • Subramanya K. Shastry
Session 4: System Control
Part of the Lecture Notes in Computer Science book series (LNCS, volume 24)


This paper describes a control structure for the control of parallel processors such that (1) at most one of the processors is engaged in its ‘critical section’ at any instant and (2) if a processor wants to enter a critical section it is eventually allowed to do so. The solution is described using APL programs and flowcharts. It does not assume the existence of ‘indivisible’ operations like ‘TS’ instruction of SYSTEM/360. It is observed that to control ‘N’ processors the number ‘M’ of ‘N-WAY’ switches required is given by:
$$M \geqslant 2 + \frac{{Ln{\mathbf{ }}(n - 1)}}{{Ln{\mathbf{ }}2}}$$


Control Structure Critical Section Mutual Exclusion Parallel Processor Versus Operation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1975

Authors and Affiliations

  • Subramanya K. Shastry
    • 1
  1. 1.Moore School of Electrical EngineeringUniversity of PennsylvaniaPhiladelphia

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