The implementation of APL on an associative processor
This paper describes an implementation of an APL interpreter on a hypothetical associative array processor. The processor is described along with those portions of its instruction set which relate to the associative array processing capabilities of the machine. The data representations used in the APL implementation are described, followed by descriptions of several useful service functions. An algorithm is presented for each APL operator. A general evaluation of the performance of this implementation is made, followed by a technique for producing detailed performance estimates from trace information. A detailed performance analysis of each APL operator is provided for this purpose.
KeywordsField Specification Element Number Parallel Processor Machine Instruction Index Pair
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