Two-Criterion Optimization in State Assignment for Synchronous Finite State Machines using NSGA-II
One of the challenging problems in circuit implementations is finding the best state assignment for implementing a synchronous sequential circuit which are also represented as Finite State Machines. This problem, commonly known as State Assignment Problem (S.A.P.), has been studied extensively because of its importance in reducing the cost of implementation of circuits. The previous work on this problem assumes the number of coding bits as constant, making it a single objective problem with the only objective being to reduce the cumulative cost of transition between the connected states.
In this work, we add another dimension to this optimization problem by introducing a second objective of minimizing the number of bits used for assignment. This is desirable to reduce the complexity and the cost of a circuit. The two objectives are conflicting and thus the optimal solution requires a tradeoff. We present an evoluationary algorithms based approach to solve this multi-dimensional optimization problem. We compare the results from two algorithms, and find that an NSGA-II based approach, with some modifications to constraint handling, gives better results and running time than NSGA. We also gain some insights about the shape of the efficient frontier.
KeywordsFinite State Machine State Assignment Efficient Frontier Sequential Machine Programmable Logic Array
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