Parallel Placement Procedure based on Distributed Genetic Algorithms

  • Masaya Yoshikawa
  • Takeshi Fujino
  • Hidekazu Terai
Conference paper


This paper discusses a novel performance driven placement technique based on distributed Genetic Algorithms, and focuses particularly on the following points:(l) The algorithm has two-level hierarchical structure consisting of outline placement and detail placement. (2) For selection control, which is one of the genetic operations, new multi-objective functions are introduced. (3) In order to reduce the computation time, a parallel processing is introduced. Results show improvement of 22.5% for worst path delay, 11.7% for power consumption, 15.9% for wire congestion and 10.7% for chip area.


Power Consumption Steiner Tree Chip Area Ring Topology Lethal Gene 
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Copyright information

© Springer-Verlag/Wien 2005

Authors and Affiliations

  • Masaya Yoshikawa
    • 1
  • Takeshi Fujino
    • 1
  • Hidekazu Terai
    • 1
  1. 1.Department of VLSI System DesignRitsumeikan UniversityJapan

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