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On the Implementation of Parallel Shortest Path Algorithms on a Supercomputer

  • Gabriele Di Stefano
  • Alberto Petricola
  • Christos Zaroliagis
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4330)

Abstract

We investigate the practical merits of a parallel priority queue through its use in the development of a fast and work-efficient parallel shortest path algorithm, originally designed for an EREW PRAM. Our study reveals that an efficient implementation on a real supercomputer requires considerable effort to reduce the communication performance (which in theory is assumed to take constant time). It turns out that the most crucial part of the implementation is the mapping of the logical processors to the physical processing nodes of the supercomputer. We achieve the requested efficient mapping through a new graph-theoretic result of independent interest: computing a Hamiltonian cycle on a directed hyper-torus. No such algorithm was known before for the case of directed hypertori. Our Hamiltonian cycle algorithm allows us to considerably improve the communication cost and thus the overall performance of our implementation.

Keywords

Hamiltonian Cycle Priority Queue Short Path Problem Sequential Algorithm Single Instruction Multiple Data 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Gabriele Di Stefano
    • 1
  • Alberto Petricola
    • 1
  • Christos Zaroliagis
    • 2
  1. 1.Dipartimento di Ingegneria Elettrica e dell’InformazioneUniversità dell’AquilaItaly
  2. 2.Computer Technology Institute and University of PatrasGreece

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