Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels

  • Hiroki Matsutani
  • Michihiro Koibuchi
  • Hideharu Amano
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4330)


In the case of simple tile-based architecture, such as small reconfigurable processor arrays, a virtual-channel mechanism, which requires additional logic and pipeline stages, will be one of the crucial factors for a low cost implementation of their on-chip routers. To guarantee deadlock-free packet transfer with no virtual channels on tori, we propose a non-minimal strategy consistent with the rule of dimension-order routing (DOR) algorithm. Since embedded streaming applications usually generate predictable data traffic, the path set can be customized to the traffic from alternative DOR paths. Although the proposed strategy does not use any virtual channels, it achieves almost the same performance as virtual-channel routers on tori in eleven of 18 application traces.


Destination Node Intermediate Node Alternative Path Virtual Channel Application Trace 
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  1. 1.
    Benini, L., Micheli, G.D.: Networks on Chips: A New SoC Paradigm. IEEE Computer 35(1), 70–78 (2002)Google Scholar
  2. 2.
    Dally, W.J., Towles, B.: Route Packets, Not Wires: On-Chip Interconnection Networks. In: Proceedings of the Design Automation Conference, pp. 684–689 (2001)Google Scholar
  3. 3.
    Burger, D., et al.: Scaling to the End of Silicon with EDGE Architectures. IEEE Computer 37(7), 44–55 (2004)MathSciNetGoogle Scholar
  4. 4.
    Liang, J., et al.: An Architecture and Compiler for Scalable On-Chip Communication. IEEE Transactions on Very Large Scale Integration Systems 12(7), 711–726 (2004)CrossRefGoogle Scholar
  5. 5.
    Taylor, M.B., et al.: The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs. IEEE Micro 22(2), 25–35 (2002)CrossRefGoogle Scholar
  6. 6.
    Matsutani, H., Koibuchi, M., Amano, H.: A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. In: Proceedings of the International Conference on Parallel and Distributed Computing Systems, pp. 24–31 (2006)Google Scholar
  7. 7.
    Flich, J., Lopez, P., Malumbres, M.P., Duato, J.: Boosting the Performance of Myrinet Networks. IEEE Transactions on Parallel and Distributed Systems 13(7), 693–709 (2002)CrossRefGoogle Scholar
  8. 8.
    Puente, V., Beivide, R., Gregorio, J.A., Prellezo, J.M., Duato, J., Izu, C.: Adaptive Bubble Router: A Design to Improve Performance in Torus Networks. In: Proceedings of the International Conference on Parallel Processing, pp. 58–67 (1999)Google Scholar
  9. 9.
    Dally, W.J., Towles, B.: Principles and Practices of Interconnection Networks. Morgan Kaufmann, San Francisco (2004)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Hiroki Matsutani
    • 1
  • Michihiro Koibuchi
    • 2
  • Hideharu Amano
    • 1
  1. 1.Keio UniversityYokohamaJapan
  2. 2.National Institute of Informatics (NII)TokyoJapan

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