A Hardware NIC Scheduler to Guarantee QoS on High Performance Servers

  • J. M. Claver
  • M. Canseco
  • P. Agustí
  • G. León
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4330)


In this paper we present the architecture and implementation of a hardware NIC scheduler to guarantee QoS on servers for high speed LAN/SAN. Our proposal employs a programmable logic device based on an FPGA in order to store and update connection states, and to decide what data stream is to be sent next. The network architecture is connection-oriented and reliable, based on credit flow control. The architecture scales from 4 to 32 streams using a Xilinx Virtex 2000E. It supports links with speeds in the order of Gbps while, maintaining the delay and jitter constrains for the QoS streams.


Virtual Channel Good Effort Priority Vector Host Processor Network Processor 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • J. M. Claver
    • 1
  • M. Canseco
    • 1
  • P. Agustí
    • 1
  • G. León
    • 1
  1. 1.Department of Computer Science and EngineeringUniversity Jaume ICastellónSpain

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