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Supporting Speculative Multithreading on Simultaneous Multithreaded Processors

  • Venkatesan Packirisamy
  • Shengyue Wang
  • Antonia Zhai
  • Wei-Chung Hsu
  • Pen-Chung Yew
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4297)

Abstract

Speculative multithreading is a technique that has been used to improve single thread performance. Speculative multithreading architectures for Chip multiprocessors (CMPs) have been extensively studied. But there have been relatively few studies on the design of speculative multithreading for simultaneous multithreading (SMT) processors. The current SMT based designs – IMT [9] and DMT [2] use load/store queue (LSQ) to perform dependence checking. Since the size of the LSQ is limited, this design is suitable only for small threads. In this paper we present a novel cache-based architecture support for speculative simultaneous multithreading which can efficiently handle larger threads. In our architecture, the associativity in the cache is used to buffer speculative values. Our 4-thread architecture can achieve about 15% speedup when compared to the equivalent superscalar processors and about 3% speedup on the average over the LSQ-based architectures, however, with a less complex hardware. Also our scheme can perform 14% better than the LSQ-based scheme for larger threads.

Keywords

Cache Line Speculative Load Chip Multiprocessor Speculative Thread Dependence Violation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Venkatesan Packirisamy
    • 1
  • Shengyue Wang
    • 1
  • Antonia Zhai
    • 1
  • Wei-Chung Hsu
    • 1
  • Pen-Chung Yew
    • 1
  1. 1.Department of Computer ScienceUniversity of MinnesotaMinneapolis

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