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Trade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors

  • Joseph Sharkey
  • Nayef Abu-Ghazeleh
  • Dmitry Ponomarev
  • Kanad Ghose
  • Aneesh Aggarwal
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4297)

Abstract

CMOS downscaling trends, manifested in the use of smaller transistor feature sizes and lower supply voltages, make microprocessors more and more vulnerable to transient errors with each new technology generation. One architectural approach to detecting and recovering from such errors is to execute two copies of the same program and then compare the results. While comparing only the store instructions is sufficient for error detection, register values also have to be compared to support fault recovery. In this paper, we propose novel checkpoint-assisted mechanisms for efficient fault recovery that dramatically reduce the number of register values to be compared for detecting soft errors and perform comprehensive investigation of these and other existing recovery schemes from the standpoint of performance, power and design complexity.

Keywords

Register File Cache Line Soft Error Transient Fault Main Thread 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Joseph Sharkey
    • 1
  • Nayef Abu-Ghazeleh
    • 1
  • Dmitry Ponomarev
    • 1
  • Kanad Ghose
    • 1
  • Aneesh Aggarwal
    • 2
  1. 1.Department of Computer Science 
  2. 2.Department of Electrical EngineeringState University of New York at Binghamton 

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