Throughput Aware Mapping for Network on Chip Design of H.264 Decoder
Network-on-Chip (NoC) has been proposed as a new methodology for addressing the design challenges of future massly integrated system in nanoscale. In this paper, we present the queuing theory based model for router to evaluate the performance of NoC in terms of drop probability, throughput and energy consumption. Then we apply the linear programming to optimize the allocation of the heterogeneously functional blocks (IPs) onto the given heterogeneous NoC architecture so as to obtain the maximum throughput as well as to optimize the energy dissipation of whole system. Finally, the three differently heterogenous Tree-based network topologies are proposed as the NoC architectures for the study case of H.264 Decoder. This paper also evaluates the proposed topologies by comparing them to other conventional topologies such as 2-D Mesh and Fat-Tree with respects to throughput, power consumption and size. We use the power modelling tool, known as Orion model to calculate the static powers, areas, and dynamic powers of three topologies. The experiment results show that our Tree-based topologies offer similar throughputs as Fat-Tree does and much higher throughputs compared to 2-D Mesh while use less chip areas and energy consumptions.
KeywordsInput Port Network Throughput Chip Design Orion Model Crossbar Switch
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- 1.ITRS. International technology roadmap for semiconductors (2005), http://public.itrs.net/
- 2.Benini, L., DeMicheli, G.: Networks On Chips: A new SoC paradigm. IEEE computer (January 2002)Google Scholar
- 4.Guerrier, P., Grenier, A.: A generic architecture for on-chip packet-switched interconnectio. In: Design automation and test in Europe conference, August 2000, pp. 250–256 (2000)Google Scholar
- 5.Kumar, S., et al.: A Network on Chip Architecture and Design Methodology. In: Proc. Int’l Symp. VLSI, pp. 117–124 (2002)Google Scholar
- 6.Hu, J., et al.: Exploiting the Routing Flexibility for Energy Performance Aware Mapping of Regular NoC Architectures. In: Proc. Design, Automation and Test in Europe Conf. (March 2003)Google Scholar
- 7.Hu, J., et al.: Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints. In: Proc. Design Automation and Test in Europe Conf. (February 2004)Google Scholar
- 8.Murali, S., et al.: Bandwidth-Constrained Mapping of Cores onto NoC Architectures. In: DATE, International Conference on Design and Test Europe, pp. 896–901 (2004)Google Scholar
- 9.Hwang, H.S., et al.: Orion: A Power Performance Simulator for Interconnection Networks. IEEE Micro (November 2002)Google Scholar
- 11.Dally, W.J., Towles, B.: Route Packets, Not Wires: On Chip Interconnection Networks. In: DAC, pp. 684–689 (2001)Google Scholar
- 14.Dally, W.J., Towles, B.: Route Packets, Not Wires: On-Chip Interconnection Networks. In: Proceedings of the 38th DAC (June 2001)Google Scholar
- 15.Nurmi, J.: Network-on-Chip: A New Paradigm for System-on-Chip Design. In: Proceedings of International Symposium on System-on-Chip (November 2005)Google Scholar