A Real-Time and Parametric Parallel Video Compression Architecture Using FPGA
This paper presents a novel parallel architecture which performs a streamed-based processing of the two-dimensional Discrete Cosine Transform (2D-DCT) for real time video compression applications. This proposal consists in using a programmable device, such as FPGA, to implement kernels of one-dimensional DCT (1D-DCT), referred to as DCT-kernels, which can be instantiated, so many as necessary, to attend the required pixel rate for a specific purpose. The implementation of the architecture proposed for the DCT-kernel also presents some interesting features that represent an advantage over the classical architectures for 1D-DCT available in the literature, mainly when a parallel architecture is supposed to use some of them. Two different applications, standard definition television (SDTV) and high definition television (HDTV), have employed the proposed parallel architecture using different number of DCT-kernels in order to show the potential of its use and real possibilities of enlarging the set of candidate applications.
KeywordsDiscrete Cosine Transform Clock Cycle Parallel Architecture Video Compression Kernel Structure
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