Parallel Image Segmentation in Reconfigurable Chip Multiprocessors
Current image segmentation implementations are not optimized to all kinds of applications. To attend the different application kinds, the solution should allow to be reconfigured to fit their different characteristics and resource needs and to improve performance. Our objective is to present an image segmentation architecture and its implementation that can be reconfigured to execute different application workloads with demanded performance. In order to achieve this objective, our proposal is a parallel image segmentation implementation, which maps a pipelined parallel segmentation software architecture to a reconfigurable pipeline structure composed of reconfigurable chip multiprocessors (RCMPs). In this work, each pipeline stage was composed of a RCMP. Our results and its analysis show that our segmentation implementation provides greater flexibility and scalability and still obtains performance gain when compared to a multiprocessor machine. The main contribution is speedup, scalability and flexibility of the proposed solution.
KeywordsImage Segmentation Software Architecture Hardware Architecture Pipeline Stage Direct Memory Access
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- 2.DeSouza, G., Kak, A.C.: Vision for Mobile Robot Navigation: A Survey. IEEE Transactions on Pattern Analysis and Machine Intelligence, 237–267 (2002)Google Scholar
- 3.Strollo, A.G.M., Napoli, E., De Caro, D., Saggese, G.P.: A Reconfigurable 2D Convolver for Real-Time SAR Imaging. In: Proceedings of the 8th IEEE International Conference on Electronics, Circuits and Systems, pp. 741–744 (2001)Google Scholar
- 4.Penha, D.O., Corrêa, J.B.T., Góes, L.F.W., Ramos, L.E.S., Pousa, C.V.P., Martins, C.A.P.S.: Comparative analysis of multi-threading on different operating systems applied on digital image processing. In: Proceedings of 3rd CSITEA (2003)Google Scholar
- 5.Hamdi, M., Lee, C.: Efficient Image Processing Applications on a Network of Workstations. In: Proceedings of the 4th IEEE Computer Architectures for Machine Perception (1995)Google Scholar
- 6.Hammond, L., Basem, A.N., Olukotun, K.: A Single-Chip Multiprocessor. Computer Magazine 30(9), 79–85 (1997)Google Scholar
- 7.McBader, S., Lee, P.: An FPGA Implementation of a Flexible, Parallel Image Processing Architecture Suitable for Embedded Vision Systems. Proceedings of the 17th International Parallel and Distributed Processing Symposium - IPDPS, 228 (2003)Google Scholar
- 9.Fonte Boa, R., Penha, D.O., Amaral, A.M., Souza, M.O.S., Martins, C.A.P.S., Ekel, P.Y.: RCMP: A Reconfigurable Chip-Multiprocessor Architecture. In: Proceedings of the Frontier on High Performance Computing and Networking (ISPA 2006) (to appear, 2006)Google Scholar