Abstract
Current image segmentation implementations are not optimized to all kinds of applications. To attend the different application kinds, the solution should allow to be reconfigured to fit their different characteristics and resource needs and to improve performance. Our objective is to present an image segmentation architecture and its implementation that can be reconfigured to execute different application workloads with demanded performance. In order to achieve this objective, our proposal is a parallel image segmentation implementation, which maps a pipelined parallel segmentation software architecture to a reconfigurable pipeline structure composed of reconfigurable chip multiprocessors (RCMPs). In this work, each pipeline stage was composed of a RCMP. Our results and its analysis show that our segmentation implementation provides greater flexibility and scalability and still obtains performance gain when compared to a multiprocessor machine. The main contribution is speedup, scalability and flexibility of the proposed solution.
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Fonte Boa, R., Penha, D.O., Amaral, A.M., Souza, M.O.S., Martins, C.A.P.S., Ekel, P.Y.: RCMP: A Reconfigurable Chip-Multiprocessor Architecture. In: Proceedings of the Frontier on High Performance Computing and Networking (ISPA 2006) (to appear, 2006)
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Boa, R.F., Amaral, A.M., da Penha, D.O., da Silva Martins, C.A.P., Ekel, P.Y. (2006). Parallel Image Segmentation in Reconfigurable Chip Multiprocessors. In: Min, G., Di Martino, B., Yang, L.T., Guo, M., Rünger, G. (eds) Frontiers of High Performance Computing and Networking – ISPA 2006 Workshops. ISPA 2006. Lecture Notes in Computer Science, vol 4331. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11942634_75
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DOI: https://doi.org/10.1007/11942634_75
Publisher Name: Springer, Berlin, Heidelberg
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