Pseudo Share Data Cache in Multiprocessor: PSDMP

  • Pengyong Ma
  • Xiao Hu
  • Shuming Chen
  • Yang Guo
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4331)


With the development of semiconductor technology, multicore is integrated on one chip [1]. In CMP, more than one core accessing the shared data will cause memory access conflict and the problem of cache coherence. Cache coherence is a precondition for the system to function correctly. So it is a key problem in CMP. In this paper, we propose a new pseudo sharing level one data cache in a chip multiprocessor architecture (PSDMP). In PSDMP, the request of memory access will be propagated on a ring chain. This method can reduce both the complexity of the design and the load of L2 cache. Simulation results show that performance of PSDMP improves about 30% averagely than another CMP which uses MESI protocol, especially the best is about 100% for the parallel applications which has many inter-processor communications for modifying shared data. In one word, PSDMP is promising processor architecture.


Data Cache Cache Line Ring Chain Response Word Cache Coherence 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Zhimin, T.: Prospect of tera-scale microprocessors. Information Technology Letters 8 (2004)Google Scholar
  2. 2.
    Li, F., Ji-lu, C., Zhen-bo, Z.: Establishment of LC memory model and Cache consistency protocol. Journal of North China Electric Power University (October 2002)Google Scholar
  3. 3.
    Viswanath, V.: Multi-log Processor Towards Scalable Event Driven Multiprocessors. In: DSD 2004 (2004)Google Scholar
  4. 4.
    Suh, T.: Supporting Cache Coherence in Heterogeneous Multiprocessor Systems. In: DATE 2004 (2004)Google Scholar
  5. 5.
    Sorin, D.J.: Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol. IEEE Transactions on Parallel and Distributed Systems 13(6) (June 2002)Google Scholar
  6. 6.
    Gao, G.R., Sarkar, V.: Location Consistency-A New Memory Model and Cache Consistency Protocol. IEEE Transactions on Computers 49(8) (August 2000)Google Scholar
  7. 7.
    Jiang-Hua, W., Shu-Ming, C.: MOSI: a SMT Microarchitecture Based On VLIW Processors. Chinese Journal of Computer 39 (2006)Google Scholar
  8. 8.
    Shuming, C., Zhentao, L.: Research and Development of High Performance YHFT Digital Signal Processor. Journal of Computer Research and Development 43 (2006)Google Scholar
  9. 9.
    Pengyong, M., Shuming, C., Guokuan, L.: The Design of Cache Controller Supporting Two Parallel Cache Accesses. High Technology Letters (2002)Google Scholar
  10. 10.
    Dan-Yu, Z., Peng-Yong, M.A., Shu-Ming, C.: The Mechanism of Miss Pipeline Cache Controller based on Two Class VLIW Architecture. Journal of Computer Research and Development (2005)Google Scholar
  11. 11.
    Guang-Qi, H., Zi-Mu, L., Xing-Ming, Z., Yong, D.: Shared Multi Ported Data Cache Architecture: SMPDCA. Chinese Journal of Computer (December 2001)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Pengyong Ma
    • 1
  • Xiao Hu
    • 1
  • Shuming Chen
    • 1
  • Yang Guo
    • 1
  1. 1.School of Computer Science and TechnologyNational University of Defense TechnologyChangshaChina

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