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Pseudo Share Data Cache in Multiprocessor: PSDMP

  • Pengyong Ma
  • Xiao Hu
  • Shuming Chen
  • Yang Guo
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4331)

Abstract

With the development of semiconductor technology, multicore is integrated on one chip [1]. In CMP, more than one core accessing the shared data will cause memory access conflict and the problem of cache coherence. Cache coherence is a precondition for the system to function correctly. So it is a key problem in CMP. In this paper, we propose a new pseudo sharing level one data cache in a chip multiprocessor architecture (PSDMP). In PSDMP, the request of memory access will be propagated on a ring chain. This method can reduce both the complexity of the design and the load of L2 cache. Simulation results show that performance of PSDMP improves about 30% averagely than another CMP which uses MESI protocol, especially the best is about 100% for the parallel applications which has many inter-processor communications for modifying shared data. In one word, PSDMP is promising processor architecture.

Keywords

Data Cache Cache Line Ring Chain Response Word Cache Coherence 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Pengyong Ma
    • 1
  • Xiao Hu
    • 1
  • Shuming Chen
    • 1
  • Yang Guo
    • 1
  1. 1.School of Computer Science and TechnologyNational University of Defense TechnologyChangshaChina

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