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RCMP: A Reconfigurable Chip-Multiprocessor Architecture

  • Raphael Fonte Boa
  • Dulcinéia Oliveira da Penha
  • Alexandre Marques Amaral
  • Márcio Oliveira Soares de Souza
  • Carlos Augusto P. da Silva Martins
  • Petr Yakovlevitch Ekel
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4331)

Abstract

Current parallel architectures are not optimized to all different kinds of applications since they can vary in requirements and resource needs. An ideal system to attend different applications should be able to fit their different characteristics and resource needs and to improve application performance. Our objective is to design and to develop a system architecture that can be reconfigured to fulfill many kinds of the application requirements and run with a reduced communication overhead. Our main goal is a new Reconfigurable Chip-MultiProcessor architecture that improves adaptability to have better performance, regardless of the application requirements. Our results and its analysis show that our architecture provides greater flexibility and scalability and still obtains performance gain over one multiprocessor architecture. Our main contribution is a Reconfigurable Chip-Multiprocessor architecture, composed of reconfigurable processing, storage and interconnection elements.

Keywords

Storage Element Convolution Operation Architectural Element 512x512 1024x1024 2048x2048 Multiprocessor Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Raphael Fonte Boa
    • 1
  • Dulcinéia Oliveira da Penha
    • 1
  • Alexandre Marques Amaral
    • 1
  • Márcio Oliveira Soares de Souza
    • 1
  • Carlos Augusto P. da Silva Martins
    • 1
  • Petr Yakovlevitch Ekel
    • 1
  1. 1.Pontifical Catholic University of Minas Gerais (Brazil) 

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