Deterministic Dynamic Monitors for Linear-Time Assertions

  • Roy Armoni
  • Dmitry Korchemny
  • Andreas Tiemeyer
  • Moshe Y. Vardi
  • Yael Zbar
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4262)


We describe a framework for dynamic verification of temporal assertions based on assertion compilation into deterministic automata. The novelty of our approach is that it allows efficient dynamic verification of general linear temporal formulas written in formal property specification languages such as LTL, ForSpec, PSL, and SVA, while the existing approaches are applicable to limited subsets only. We also show an advantage of the described framework over industrial simulators, which typically use transaction-based verification. Another advantage of our approach is its ability to use deterministic checkers directly for hardware emulation. Finally, we compare the deterministic compilation with the OBDD-based on-the-fly simulation of deterministic automata. We show that although the OBDD-based simulation method is much slower, the two methods may be efficiently combined for hybrid simulation, when the RTL signals in assertions are mixed with symbolic variables.


Model Check Linear Temporal Logic Register Transfer Level Linear Temporal Logic Formula Deterministic Automaton 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Roy Armoni
    • 1
  • Dmitry Korchemny
    • 1
  • Andreas Tiemeyer
    • 1
  • Moshe Y. Vardi
    • 2
  • Yael Zbar
    • 1
  1. 1.Intel 
  2. 2.Rice University and Microsoft Research 

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