Abstract
This paper presented the smallest hardware architecture of the ARIA block cipher algorithm. A 128-bit data block was divided into eight 16-bit blocks to reduce the hardware size. The 16-bit architecture allowed two S-Boxes and 16-bit diffusion operation. We proposed a design for the substitution layer and the memory block. The proposed round key generator processed a 16-bit block of a 128-bit round key for three cycles. The proposed ARIA module with a 128-bit key comprised 6,076 equivalent gates using a 0.18-μm CMOS standard cell library. It took 88 clock cycles to generate four initial values for a round key and 400 clock cycles to en/decrypt 128-bit block data. The power consumption of 16-bit ARIA was only 5.02 μW at 100 kHz 1.8V.
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Yang, S., Park, J., You, Y. (2006). The Smallest ARIA Module with 16-Bit Architecture. In: Rhee, M.S., Lee, B. (eds) Information Security and Cryptology – ICISC 2006. ICISC 2006. Lecture Notes in Computer Science, vol 4296. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11927587_11
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DOI: https://doi.org/10.1007/11927587_11
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-49112-5
Online ISBN: 978-3-540-49114-9
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