Low Power AES Hardware Architecture for Radio Frequency Identification

  • Mooseop Kim
  • Jaecheol Ryou
  • Yongje Choi
  • Sungik Jun
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4266)


We present a new architecture of Advanced Encryption Standard (AES) cryptographic hardware which can be used as cryptographic primitives supporting privacy and authentication for Radio Frequency Identification (RFID). RFID is a technology to identify goods or person containing the tags. While it is a convenient way to track items, it also provides chances to track people and their activities through their belongings. For these reasons, privacy and authentication are a major concern with RFID system and many solutions have been proposed. M. Feldhofer , S. Dominikus, and J. Wolkerstorfer introduced the Interleaved Protocol which serves as a means of authenticating RFID tag to reader devices in [14]. They designed very small and low power AES hardware as a cryptographic primitive. In this contribution, we introduce a novel method to increase the operating speed of previous method for low power AES cryptographic circuits. Our low power AES cryptographic hardware can encrypt 128-bit data block within 870 clock cycles using less than 4000 gates and has a power consumption about or less than 20 μW on a 0.25 μm CMOS process.


Clock Cycle Advance Encryption Standard Data Path Advance Encryption Standard Algorithm Functional Step 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Mooseop Kim
    • 1
  • Jaecheol Ryou
    • 2
  • Yongje Choi
    • 1
  • Sungik Jun
    • 1
  1. 1.Electronics and Telecommunications Research Institute (ETRI)DaejeonSouth Korea
  2. 2.Division of Electrical and Computer EngineeringChungnam National UniversityDaejeonSouth Korea

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