Low-Cost Microarchitectural Techniques for Enhancing the Prediction of Return Addresses on High-Performance Trace Cache Processors

  • Yunhe Shi
  • Emre Özer
  • David Gregg
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4263)


This paper discusses the effects of the prediction of return addresses in high-performance processors designed with trace caches. We show that a traditional return address stack used in such a processor predicts return addresses poorly if a trace cache line contains a function call and a return. This situation can often be observed for processors demanding aggressive instruction fetch bandwidth. Thus, we propose two potential schemes to improve the prediction accuracy of return addresses. We demonstrate that the proposed schemes increase the return address prediction rates reasonably using minimal hardware support. We also analyze the effects of various trace cache configurations on the return address prediction accuracy such as trace cache set associativity, cache size and line size. Our experimental results show that the average return address prediction accuracy across several benchmarks can be up to 11% better than a traditional return address stack in a high-performance processor with a trace cache.


Function Call Cache Size Cache Line Return Address Return Instruction 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Patel, S.J.: Trace Cache Design for Wide-Issue Superscalar Processor. PhD thesis, Computer Science and Engineering in The University of Michigan (1999)Google Scholar
  2. 2.
    Jacobson, Q., Rotenberg, E., Smith, J.: Path-based next trace prediction. In: Proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture (1997)Google Scholar
  3. 3.
    Rotenberg, E., Bennett, S., Smith, J.E.: A trace cache microarchitecture and evaluation. IEEE Transactions on Computers (1999)Google Scholar
  4. 4.
    Santana, O.J., Falcon, A., Ramirez, A., Larriba-Pey, J.L., Valero, M.: Next stream prediction. Technical Report UPC-DAC-2002-15, Technical Report (2002)Google Scholar
  5. 5.
    Webb, C.F.: Subroutine call/return stack. IBM Tech. Disc. Bulletin 30(11) (1988)Google Scholar
  6. 6.
    Kaeli, D.R., Emma, P.G.: Branch history table prediction of moving target branches due to subroutine returns. In: Proceedings of the 18th Annual International Symposium on Computer Architecture (ISCA-18) (1991)Google Scholar
  7. 7.
    Skadron, K., Ahuja, P.S., Martonosi, M., Clark, D.W.: Improving prediction for procedure returns with return-address-stack repair mechanisms. In: Proceedings of the 31st Annual ACM/IEEE International Symposium on Microarchitecture (1998)Google Scholar
  8. 8.
    Jourdan, S., Stark, J., Hsing, T.H., Patt, Y.N.: Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution. International Journal of Parallel Programming 25(5) (1997)Google Scholar
  9. 9.
    Hily, S., Seznec, A.: Branch prediction and simultaneous multithreading. In: Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques (PACT 1996) (1996)Google Scholar
  10. 10.
    Zahran, M.M., Franklin, M.: Return-address prediction in speculative multithreaded environments. In: Proceedings of the 9th International Conference on High Performance Computing (2002)Google Scholar
  11. 11.
    KleinOsowski, A.J., Lilja, D.J.: Minnespec: A new spec benchmark workload for simulation-based computer architecture research. Computer Architecture Letters 1 (2002)Google Scholar
  12. 12.
    Austin, T., Larson, E., Ernst, D.: Simplescalar: An infrastructure for computer system modeling. Computer, pp. 59–67 (2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Yunhe Shi
    • 1
  • Emre Özer
    • 2
  • David Gregg
    • 1
  1. 1.Department of Computer ScienceTrinity College Dublin 
  2. 2.ARM Ltd.CambridgeUK

Personalised recommendations