Verification Challenges and Opportunities in the New Era of Microprocessor Design

  • Jin Yang
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4218)


Microprocessor design continues to be driven by the economics of Moore’s Law. Each new process generation doubles the number of transistors available to microprocessor architects and designers. Design complexity continues to increase, and so does verification complexity, in order to keep microprocessor performance scaling up with Moore’s Law. Moving forward, we are facing even tougher challenges associated with the power scaling and reliability issues of future transistor devices. To build high performance, power efficient, reliable microprocessors using unreliable devices, we have to take a holistic approach, and deliver innovative technology solutions across the entire stack: circuit, micro-architecture, architecture, platform, and embedded software. Here we examine several future design trends and their implications on verification.


Soft Error Embed Software Level Parallelism Power Scaling Power Management Scheme 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Jin Yang
    • 1
  1. 1.Validation Research Lab.Intel Corporation 

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