Advertisement

Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis

  • Tomohiro Yoneda
  • Chris J. Myers
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4218)

Abstract

This paper presents a way to contract timed STGs effectively for a decomposition based logic synthesis of timed circuits. In the decomposition based synthesis method, a sufficient input signal set for each output is first obtained, and the timed STG is contracted to include only transitions on this input signal set and the output of interest, from which the circuit for the output is synthesized. Care is, however, needed for the contraction of timed STGs. A simple contraction algorithm used for the untimed version can result in the loss of important timing information, causing it to synthesize non-optimal circuits. On the other hand, exact contraction that preserves the timing information precisely is applied only to a small class of transitions, which degrades the performance of the decomposition based synthesis method. This paper proposes a way to contract timed STGs effectively without losing the optimality of the synthesized circuits, and shows some experimental results.

Keywords

Discrete Cosine Transform Output Transition Time Bound Trigger Transition Context Signal 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Cortadella, J., Kishinevsky, M., Kondratyev, A., Lavagno, L., Yakovlev, A.: Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IEICE Trans. on Information and Systems E80-D(3), 315–325 (1997)Google Scholar
  2. 2.
    Beerel, P.A., Myers, C.J., Meng, T.H.-Y.: Covering conditions and algorithms for the synthesis of speed-independent circuits. IEEE Trans. on Computer-Aided Design (1998)Google Scholar
  3. 3.
    Fuhrer, R.M., Nowick, S.M., Theobald, M., Jha, N.K., Lin, B., Plana, L.: Minimalist: An environment for the synthesis, verification and testability of burst-mode asynchronous machines. Technical Report TR CUCS-020-99, Columbia University, NY (1999)Google Scholar
  4. 4.
    Chu, T.-A.: Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications. PhD thesis, MIT Laboratory for Computer Science (1987)Google Scholar
  5. 5.
    Yoneda, T., Onda, H., Myers, C.: Synthesis of speed independent circuits based on decomposition. In: Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 135–145. IEEE Computer Society Press, Los Alamitos (2004)Google Scholar
  6. 6.
    Carmona, J., Cortadella, J.: ILP models for the synthesis of asynchronous control circuits. In: Proc. of the IEEE/ACM International Conference on Computer Aided Design, pp. 818–825 (2003)Google Scholar
  7. 7.
    Stevens, K., Rotem, S., Ginosar, R., Beerel, P., Myers, C., Yun, K., Kol, R., Dike, C., Roncken, M.: An asynchronous instruction length decoder. IEEE Journal of Solid-State Circuits 35(2), 217–228 (2001)CrossRefGoogle Scholar
  8. 8.
    Sutherland, I., Fairbanks, S.: GasP: A minimal FIFO control. In: Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 46–53. IEEE Computer Society Press, Los Alamitos (2001)Google Scholar
  9. 9.
    Yoneda, T., Myers, C.: Synthesis of timed circuits based on decomposition. NII Technical Report, NII-2006-001E (2006)Google Scholar
  10. 10.
    Suzuki, I., Murata, T.: Stepwise refinements for transitions and places. Springer, New York (1982)Google Scholar
  11. 11.
    Berthelot, G.: Checking properties of nets using transformations. In: Rozenberg, G. (ed.) APN 1985. LNCS, vol. 222, pp. 19–40. Springer, Heidelberg (1986)CrossRefGoogle Scholar
  12. 12.
    Murata, T.: Petri nets: Properties, analysis, and applications. Proceedings of the IEEE 77(4), 541–580 (1989)CrossRefGoogle Scholar
  13. 13.
    Vogler, W., Wollowski, R.: Decomposition in asynchronous circuit design. In: Cortadella, J., Yakovlev, A., Rozenberg, G. (eds.) Concurrency and Hardware Design. LNCS, vol. 2549, pp. 152–190. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  14. 14.
    Zheng, H., Mercer, E., Myers, C.J.: Modular verification of timed circuits using automatic abstraction. IEEE Trans. on Computer-Aided Design 22(9) (2003)Google Scholar
  15. 15.
    Zheng, H.: Modular Synthesis and Verification of Timed Circuits Using Automatic Abstraction. PhD thesis, University of Utah (2001)Google Scholar
  16. 16.
    Myers, C.J.: Computer-Aided Synthesis and Verification of Gate-Level Timed Circuits. PhD thesis, Dept. of Elec. Eng., Stanford University (1995)Google Scholar
  17. 17.
    Yoneda, T., Mercer, E.G., Myers, C.J.: Modular synthesis of timed circuits using partial order reduction. In: Proc. of the 10th Workshop on Synthesis And System Integration of Mixed Technologies, pp. 127–134 (2001)Google Scholar
  18. 18.
    Mercer, E.G., Myers, C.J., Yoneda, T.: Improved POSET timing analysis in timed Petri nets. In: Proc. of the 10th Workshop on Synthesis And System Integration of Mixed Technologies, pp. 151–158 (2001)Google Scholar
  19. 19.
    Georgiadis, L., Tarjan, R.E., Triantafyllis, S., August, D.: Finding dominators in practice. In: Albers, S., Radzik, T. (eds.) ESA 2004. LNCS, vol. 3221, pp. 677–688. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  20. 20.
    Yoneda, T., Matsumoto, A., Kato, M., Myers, C.: High level synthesis of timed asynchronous circuits. In: Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 178–189. IEEE Computer Society Press, Los Alamitos (2005)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Tomohiro Yoneda
    • 1
  • Chris J. Myers
    • 2
  1. 1.National Institute of Informatics 
  2. 2.University of Utah 

Personalised recommendations