Three-Phase Dual-Rail Pre-charge Logic

  • Marco Bucci
  • Luca Giancane
  • Raimondo Luzzi
  • Alessandro Trifiletti
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4249)


This paper investigates the design of a dual-rail pre-charge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place & route) without any constraint on the routing of the complementary wires. The proposed logic is based on a three phase operation where, in order to obtain a constant energy consumption over the operating cycle, an additional discharge phase is performed after pre-charge and evaluation. In this work, the proposed concept has been implemented as an enhancement of the SABL logic with a limited increase in circuit complexity. Implementation details and simulation results are reported which show a power consumption independent of the sequence of processed data and load capacitances. An improvement in the energy consumption balancing up to 100 times with respect to SABL has been obtained.


DPA dual-rail logic SABL security 


  1. 1.
    Kocher, P., Jaffe, J., Jun, B.: Differential power analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999)Google Scholar
  2. 2.
    Messerges, T.S., Dabbish, E.A., Sloan, R.H.: Examining Smart-Card Security under the Threat of Power Analysis Attacks. IEEE Trans. Computers 51(5), 541–552 (2002)CrossRefMathSciNetGoogle Scholar
  3. 3.
    Coron, J.: Resistance Against Differential Power Analysis for Elliptic Curve Cryptosystems. In: Koç, Ç.K., Paar, C. (eds.) CHES 1999. LNCS, vol. 1717, pp. 292–302. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  4. 4.
    Clavier, C., Coron, J., Dabbous, N.: Differential Power Analysis in the Presence of Hardware Countermeasures. In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 252–263. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  5. 5.
    Benini, L., Omerbegovic, E., Macii, A., Poncino, M., Macii, E., Pro, F.: Energy-aware design techniques for differential power analysis protection. In: Proc. Design Automation Conf. (DAT 2003), pp. 36–41 (2003)Google Scholar
  6. 6.
    Saputra, H., Vijaykrishnan, N., Kandemir, M., Irwin, M.J., Brooks, R., Kim, S., Zhang, W.: Masking the energy behavior of DES encryption. In: Proc. Design, Automation and Test in Europe Conf (DAT 2003), pp. 84–89 (2003)Google Scholar
  7. 7.
    Ratanpal, G.B., Williams, R.D., Blalock, T.N.: An On-Chip Suppression Countermeasure to Power Analysis Attacks. IEEE Trans. Dependable and Secure Computing 1(3), 179–189 (2004)CrossRefGoogle Scholar
  8. 8.
    Shamir, A.: Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies. In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 71–77. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  9. 9.
    Golic, J.D., Menicocci, R.: Universal Masking on Logic Gate Level. Electronics Lett. 40(9) (April 2004)Google Scholar
  10. 10.
    Bucci, M., Guglielmo, M., Luzzi, R., Trifiletti, A.: A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds.) PATMOS 2004. LNCS, vol. 3254, pp. 481–490. Springer, Heidelberg (2004)Google Scholar
  11. 11.
    Bucci, M., Guglielmo, M., Luzzi, R., Trifiletti, A.: A Countermeasure against Differential Power Analysis based on Random Delay Insertion. In: Proc. IEEE Intl. Symp. Circuits and Systems (ISCAS 2005), pp. 3547–3550 (2005)Google Scholar
  12. 12.
    Mangard, S., Popp, T., Gammel, B.M.: Side-Channel Leakage of Masked CMOS Gates. In: Menezes, A. (ed.) CT-RSA 2005. LNCS, vol. 3376, pp. 351–365. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  13. 13.
    Mangard, S., Pramstaller, N., Oswald, E.: Successfully Attacking Masked AES Hardware Implementations. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 157–171. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  14. 14.
    Tiri, K., Akmal, M., Verbauwhede, I.: A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards. In: Proc. IEEE 28th European Solid-State Circuit Conf (ESSCIRC 2002) (2002)Google Scholar
  15. 15.
    Tiri, K., Verbauwhede, I.: A Logic Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. In: Proc. Design, Automation and Test in Europe Conference and Exposition (DATE 2004), pp. 246–251 (2004)Google Scholar
  16. 16.
    Sokolov, D., Murphy, J., Bystrov, A., Yakovlev, A.: Improving the Security of Dual-Rail Circuits. In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol. 3156, pp. 282–297. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  17. 17.
    Tiri, K., Verbauwhede, I.: Place and route for secure standard cell design. In: Proc. Smart Card Research and Advanced Application IFIP Conf (CARDIS 2004) (2004)Google Scholar
  18. 18.
    Popp, T., Mangard, S.: Masked Dual-Rail Pre-Charge Logic: DPA-Resistance without Routing Constraints. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 172–186. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  19. 19.
    Popp, T., Mangard, S.: Implementation Aspects of the DPA-Resistant Logic Style MDPL. In: Proc. IEEE Intl. Symp. Circuits and Systems (ISCAS 2006) (to appear, 2006)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Marco Bucci
    • 1
  • Luca Giancane
    • 2
  • Raimondo Luzzi
    • 1
  • Alessandro Trifiletti
    • 2
  1. 1.Infineon Technologies AG 
  2. 2.University of Rome “La Sapienza” 

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