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Two-Level Dynamic Programming Hardware Implementation for Real Time Processing

  • Yong Kim
  • Hong Jeong
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4251)

Abstract

In this paper, we present an efficient architecture for connected speech recognition that can be efficiently implemented with FPGA. The architecture consists of newly derived two-level dynamic programming(TLDP) that use only bit addition and shift operations. The advantages of this architecture are the spatial efficiency to accommodate more words with limited space and the computational speed from avoiding propagation delays in multiplications. The architecture is highly regular, consisting of identical and simple processing elements with only nearest-neighbor communication, and external communication occurs with the end processing elements. In order to verify the proposed architecture, we have also designed and implemented it, prototyping with Xilinx FPGAs running at 33MHz.

Keywords

Hide Markov Model Speech Recognition Processing Element Clock Signal Reference Pattern 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Yong Kim
    • 1
  • Hong Jeong
    • 1
  1. 1.Department of Electronic and Electrical EngineeringPOSTECHPohangSouth Korea

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