On the Design and Implementation of a High Performance Configurable Architecture for Testor Identification

  • René Cumplido
  • J. Ariel Carrasco-Ochoa
  • Claudia Feregrino
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4225)


Typical testors are a useful tool to do feature selection in supervised classification problems with mixed incomplete data. However, the complexity of computing all typical testors of a training matrix has an exponential growth with respect to the number of columns in the matrix. For this reason different approaches like heuristic algorithms, parallel and distributed processing, have been developed. In this paper, we present a configurable custom architecture for the efficient identification of testors from a given input matrix. The architectural design is based on a brute force approach that is suitable for high populated input matrixes. The architecture has been designed to deal with parallel processing and can be configured for any size of matrix. The architecture is able to evaluate if a vector is a testor of the matrix in a single clock cycle. The architecture has been implemented on a Field Programmable Gate Array (FPGA) device. Results show that it provides runtime improvements over software implementations running on state-of-the-art processors. FPGA implementation results are presented and implications to the field of pattern recognition discussed.


Field Programmable Gate Array Typical Testors Register File Brute Force Approach Field Programmable Gate Array Implementation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • René Cumplido
    • 1
  • J. Ariel Carrasco-Ochoa
    • 1
  • Claudia Feregrino
    • 1
  1. 1.Computer Science DepartmentINAOETonantzintla, PueblaMéxico

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