Case Study of a Fault Attack on Asynchronous DES Crypto-Processors
This paper proposes a practical fault attack on two asynchronous DES crypto-processors, a reference version and a hardened version, using round reduction. Because of their specific architecture, asynchronous circuits have a very specific behavior in the presence of faults. Previous works show that they are an interesting alternative to design robust systems. However, this paper demonstrates that there are weaknesses left, and that we are able both to identify and exploit them. The effect of the fault is to reduce the number of rounds by corrupting the multi-rail round counter protected by alarm cells. The fault injection mean is a laser. A description of the fault injection process is presented, followed by how the results can be used to retrieve the key. Weaknesses are theoretically identified and analyzed. Finally, possible counter-measures are described.
KeywordsFault Injection Cipher Text Differential Cryptanalysis Fault Attack Asynchronous Circuit
Unable to display preview. Download preview PDF.
- 2.Choukri, H., Tunstall, M.: Round Reduction Using Faults. In: 2nd Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 2005), Edinburgh, Scotland, pp. 13–24, September 2(2005)Google Scholar
- 3.Monnet, Y., Renaudin, M., Leveugle, R., Dumont, S., Bouesse, F.: An Asynchronous DES Crypto-Processor Secured against Fault Attacks. In: International Conference on Very Large Scale Integration (VLSI-SOC), pp. 21–26 (2005)Google Scholar
- 4.Monnet, Y., Renaudin, M., Leveugle, R., Feyt, N., Moitrel, P.: Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. In: 12th IEEE International On-Line Testing Symposium (IOLTS), Lake of Como, Italy, July 10-12 (2006)Google Scholar
- 6.LaFrieda, C., Manohar, R.: Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits. In: International Conference on Dependable Systems and Networks (DSN 2004), Florence Italy, June 28 - July 01, pp. 41–50 (2004)Google Scholar
- 7.Moore, S., Anderson, R., Mullins, R., Taylor, G., Fournier, J.J.A.: Balanced self-checking asynchronous logic for smart card applications. In: Microprocessors and Microsystems, vol. 27, pp. 421–430. Elsevier Science Publishers, Amsterdam (2003)Google Scholar
- 9.Hellman, M., Langford, S.: Differential-Linear Cryptanalysis. In: Desmedt, Y.G. (ed.) CRYPTO 1994. LNCS, vol. 839, pp. 17–25. Springer, Heidelberg (1994)Google Scholar
- 10.Monnet, Y., Renaudin, M., Leveugle, R.: Hardening Techniques against Transient Faults for Asynchronous Circuits. In: 11th IEEE International On-Line Testing Symposium (IOLTS), Saint Raphael, French Riviera, France, July 6th-8th, pp. 129–134 (2005)Google Scholar