DPA on Faulty Cryptographic Hardware and Countermeasures

  • Konrad J. Kulikowski
  • Mark G. Karpovsky
  • Alexander Taubin
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4236)


Balanced gates are an effective countermeasure against power analysis attacks only if they can be guaranteed to maintain their power balance. Traditional testing and reliability methods are used primarily only to ensure the correctness of the logical functionality and not the balance of a circuit. Due to the hardware redundancy in balanced gate designs, there are many faults which can imbalance a balanced gate without causing logical errors. As a result, traditional testing and reliability methods and architectures are unable to test and verify if a gate is completely defect and fault-free and hence balanced. Our simulations show that a few faulty balanced gates can make a circuit as vulnerable to power analysis attacks as a completely imbalanced implementation. This vulnerability opens the possibility of new methods of attacks based on a combination of fault and power attacks. A solution to the vulnerability based on a built-in differential self-balance comparator is presented.


Boolean Function Advance Encryption Standard Data Encryption Standard Differential Power Analysis Fault Attack 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Tiri, K., Akmal, M., Verbauwhede, I.: A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards. In: 28th European Solid-State Circuits Conference (ESSCIRC 2002), pp. 403–406 (September 2002)Google Scholar
  2. 2.
    Mace, F., Standaert, F.X., Quisquater, J.J., Legat, J.D.: A Design Methodology for Secured ICs Using Dynamic Current Mode Logic. In: Paliouras, V., Vounckx, J., Verkest, D. (eds.) PATMOS 2005. LNCS, vol. 3728, pp. 550–560. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  3. 3.
    MacDonald, D.J.: A Balanced-Power Domino-Style Standard Cell Library for Fine-Grain Asynchronous Pipelined Design to Resist Differential Power Analysis Attacks. Master of Science Thesis, Boston University, Boston (2005), Availabe at: http://reliable.bu.edu/Pro-jects/MacDonald_thesis.pdf
  4. 4.
    Tiri, K., Verbauwhede, I.: A Logic Level Design Methodology for a Secure DPA Resis-tant ASIC or FPGA Implementation. In: Design, Automation and Test in Europe Conference (DATE 2004), pp. 246–251 (February 2004)Google Scholar
  5. 5.
    Jaffe, J., Kocher, P., Jun, B.: Hardware-level mitigation and DPA countermeasures for cryptographic devices. US Patent 6654884Google Scholar
  6. 6.
    Karpovsky, M., Kulikowski, K., Taubin, A.: Differential Fault Analysis Attack Resistant Architectures for the Advanced Encryption Standard. In: Proc. World Computing Congress, pp. 177–192 (2004)Google Scholar
  7. 7.
    Kulikowski, K., Karpovsky, M., Taubin, A.: Robust Codes for Fault Attack Resistant Cryptographic Hardware. In: Fault Diagnosis and Tolerance in Cryptography, 2nd International Workshop, Edinburgh (2005)Google Scholar
  8. 8.
    Karri, R., Kuznetsov, G., Gossel, M.: Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 113–124. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  9. 9.
    Coron, J.S., Naccache, D., Kocher, P.: Statistics and Secret Leakage. Trans. on Embedded Computing Sys. 3(3), 492–508 (2004)CrossRefGoogle Scholar
  10. 10.
    Rajsuman, R.: Iddq testing for CMOS VLSI. Proceedings of the IEEE 88(4), 544–568 (2000)CrossRefGoogle Scholar
  11. 11.
    Su, S.-T., Makki, R.Z., Nagle, T.: Transient power supply current monitoring - A new test method for CMOS VLSI circuits. Journal of Electronic Testing 6(1), 23–43 (1995)CrossRefGoogle Scholar
  12. 12.
    Gregorio, A.D.: Cryptographic Key Reliable Lifetimes: Bounding the Risk of Key Exposure in the Presence of Faults. In: FTDC 2005 (2005)Google Scholar
  13. 13.
    Canovas, C., Clediere, J.: What do S-boxes Say in Differential Side Channel Attacks? IACR e-Print archive 2005/311 (2005)Google Scholar
  14. 14.
    FIPS PUB 197: Advanced Encryption Standard, http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
  15. 15.
    Smirnov, A., Taubin, A., Karpovsky, M.: An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library. In: ACSD 2005: Fifth International Conference on Application of Concurrency to System Design (2005)Google Scholar
  16. 16.
    Smirnov, A.V., Kulikowski, K.J., Taubin, A.: Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 399–413. Springer, Heidelberg (2006)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Konrad J. Kulikowski
    • 1
  • Mark G. Karpovsky
    • 1
  • Alexander Taubin
    • 1
  1. 1.Reliable Computing LaboratoryBoston UniversityBostonUSA

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