A Low-Power CMOS Analog Neuro-fuzzy Chip
This paper proposes a low-power high-speed CMOS analog two- input/one-output neuro-fuzzy chip, the basic blocks of which are Gaussian membership function circuit, minimization circuit, and a centroid algorithm defuzzification circuit. This chip has been fabricated in 0.6-μm mixed-signal CMOS technology. Experiment and HSPICE simulation results show that because the compact structures and high-precision of the blocks the system not only consumes little power but also can be directly tuned by the weights calculated through the software such as Matlab.
KeywordsOutput Voltage Versus Versus Versus Versus Versus Versus Versus Fuzzy Logic Controller Minimization Circuit
Unable to display preview. Download preview PDF.