A Low-Power CMOS Analog Neuro-fuzzy Chip

  • Wang Wei-zhi
  • Jin Dong-ming
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4222)


This paper proposes a low-power high-speed CMOS analog two- input/one-output neuro-fuzzy chip, the basic blocks of which are Gaussian membership function circuit, minimization circuit, and a centroid algorithm defuzzification circuit. This chip has been fabricated in 0.6-μm mixed-signal CMOS technology. Experiment and HSPICE simulation results show that because the compact structures and high-precision of the blocks the system not only consumes little power but also can be directly tuned by the weights calculated through the software such as Matlab.


Output Voltage Versus Versus Versus Versus Versus Versus Versus Fuzzy Logic Controller Minimization Circuit 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Wang Wei-zhi
    • 1
  • Jin Dong-ming
    • 1
  1. 1.Institute of MicroelectronicsTsinghua UniversityBeijingChina

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