Using UML Activities for System-on-Chip Design and Synthesis

  • Tim Schattkowsky
  • Jan Hendrik Hausmann
  • Gregor Engels
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4199)


The continuous advances in manufacturing Integrated Circuits (ICs) enable complete systems on a single chip. However, the design effort for such System-on-Chip (SoC) solutions is significant. The productivity of the design teams currently lags behind the advances in manufacturing and this design productivity gap is still widening. One important reason is the lack of abstraction in traditional Hardware Description Languages (HDLs) like VHDL. The UML provides more abstract concepts for modeling behavior that can also be employed for hardware design. In particular, the new UML Activity semantics fit nicely with the inherent data flow in hardware systems. Therefore, we introduce a UML-based design approach for complete SoC specification. Our approach enables generation of complete synthesizable HDL code. The equivalent hardware can be automatically generated using the existing tools chains. As an example, we outline Handel-C code generation for an MP3 decoder design.


Unify Modeling Language Field Programmable Gate Array Class Diagram Activity Diagram Hardware Design 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    André, C., Cuccuru, S., Dekeyser, J.-L., De Simone, R., Dumoulin, C., Forget, J., Goutier, T., Gérard, S., Mallet, F., Radermachenr, A., Rioux, L., Shaunier, T., Sorel, Y.: MARTE: A New OMG Profile RFP for the Modeling and Analysis of Real-Time Embedded Systems. In: Proc. DAC Workshop UML for SoC Design (UML-SoC) 2005 (2005)Google Scholar
  2. 2.
    Bahill, A.T., Daniels, J.: Using object-oriented and UML tools for hardware design: a case study. Systems Engineering 6(1), 28–48 (2003)CrossRefGoogle Scholar
  3. 3.
    Björklund, D., Lilius, J.: From UML Behavioral Descriptions to Efficient Synthesizable VHDL. In: Proceedings of the 20th IEEE NORCHIP Conference (November 2002)Google Scholar
  4. 4.
    Balcer, M., Mellor, S.: Exploring the Role of Executable UML in Model-Driven Architecture. In: Executable UML: A Foundation for Model-Driven Architecture, Addison-Wesley, Reading (2002)Google Scholar
  5. 5.
    Celoxica: Handel-C language Overview (2002),
  6. 6.
    Damasevicius, R., Stuikys, V.: Application of UML for hardware design based on design process model. In: ASP-DAC 2004, pp. 244–249 (2004)Google Scholar
  7. 7.
    Hallal, H., Xiao-Hua, K., Negulescu, R.: Experiments in modeling integrated circuit blocks by UML. In: International Workshop on IP Based Synthesis and System Design (1999)Google Scholar
  8. 8.
    International Electrotechnical Commission: IEC 1131-3: Programmable Controllers – Part 3: Programming Languages, IEC 1131-3 (1993)Google Scholar
  9. 9.
    McUmber, W., Cheng, B.: UML-Based Analysis of Embedded Systems Using a Mapping to VHDL. In: The 4th IEEE International Symposium on High-Assurance Systems Engineering, November 17-19, pp. 56–63 (1999)Google Scholar
  10. 10.
    Martin, G., Müller, W. (eds.): UML for SoC Design. Kluwer, Dordrecht (2005)Google Scholar
  11. 11.
    Object Management Group: UML 2.0 superstructure specification (2005), Available at
  12. 12.
    Rajan, S., Hasegawa, T., Shoji, M., Zhu, Q., Tsuneo, N.: UML Profile for System-on-Chip (SoC). In: Proc. DAC Workshop UML for SoC Design (UML-SoC) 2005 (2005)Google Scholar
  13. 13.
    Schattkowsky, T., Hausmann, J.H., Rettberg, A.: Using UML Activities for Synthesis on Reconfigurable Hardware. In: Proc. DAC Workshop UML for SoC Design (UML-SoC) 2005 (2005)Google Scholar
  14. 14.
    Sinha, V., Doucet, F., Siska, C., Gupta, R., Liao, S., Ghosh, A.: YAML: a tool for hardware design visualization and capture. In: Proceedings of the 13th international symposium on System synthesis, pp. 1080–1082. IEEE Computer Society, Los Alamitos (2000)Google Scholar
  15. 15.
    Stoerrle, H.: Semantics and Verification of Data-Flow in UML 2.0 Activities. In: Proc. Intl. Ws. on Visual Languages and Formal Methods (VLFM 2004) (2004)Google Scholar
  16. 16.
    SysML Partners: SysML Specification v. 1.0a (2005), Available at
  17. 17.
    Yakovlev, A., Gomes, L., Lavagno, L. (eds.): Hardware Design and Petri Nets. Springer, Heidelberg (2000)MATHGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Tim Schattkowsky
    • 1
  • Jan Hendrik Hausmann
    • 2
  • Gregor Engels
    • 2
  1. 1.C-LabPaderbornGermany
  2. 2.University of PaderbornPaderbornGermany

Personalised recommendations