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Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata

  • Remy Chevallier
  • Emmanuelle Encrenaz-Tiphène
  • Laurent Fribourg
  • Weiwen Xu
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4202)

Abstract

Using a variant of Clariso-Cortadella’s parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of some crucial timing behaviours of the architecture of SPSMALL memory. This allows us to check two different implementations of this architecture.

Keywords

Input Signal Linear Constraint Output Port Generic Architecture Read Operation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Remy Chevallier
    • 1
  • Emmanuelle Encrenaz-Tiphène
    • 2
  • Laurent Fribourg
    • 2
  • Weiwen Xu
    • 2
  1. 1.STMicroelectronics, FTM, Central R&DCrollesFrance
  2. 2.LSV – CNRS, ENS de CachanFrance

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