Abstract
Using a variant of Clariso-Cortadella’s parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of some crucial timing behaviours of the architecture of SPSMALL memory. This allows us to check two different implementations of this architecture.
Partially supported by project MEDEA+ Blueberries.
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Chevallier, R., Encrenaz-Tiphène, E., Fribourg, L., Xu, W. (2006). Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata. In: Asarin, E., Bouyer, P. (eds) Formal Modeling and Analysis of Timed Systems. FORMATS 2006. Lecture Notes in Computer Science, vol 4202. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11867340_9
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DOI: https://doi.org/10.1007/11867340_9
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