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Simulator for Real-Time Abstract State Machines

  • Pavel Vasilyev
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4202)

Abstract

We describe a concept and design of a simulator of Real-Time Abstract State Machines. Time can be continuous or discrete. Time constraints are defined by linear inequalities. Two semantics are considered: with and without non-deterministic bounded delays between actions. The simulator is easily configurable. Simulation tasks can be generated according to descriptions in a special language. The simulator will be used for on-the-fly verification of formulas in an expressible timed predicate logic. Several features that facilitate the simulation are described: external functions definition, delays settings, constraints specification, and others.

Keywords

Dynamic Function Predicate Symbol Abstract State Machine Message Queue Parallel Block 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Pavel Vasilyev
    • 1
    • 2
  1. 1.Laboratory of Algorithmics, Complexity and Logic, Department of InformaticsUniversity Paris-12France
  2. 2.Computer Science DepartmentUniversity of Saint PetersburgRussia

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