A Study of the Performance Potential for Dynamic Instruction Hints Selection

  • Rao Fu
  • Jiwei Lu
  • Antonia Zhai
  • Wei-Chung Hsu
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4186)


Instruction hints have become an important way to communicate compile-time information to the hardware. They can be generated by the compiler and the post-link optimizer to reduce cache misses, improve branch prediction and minimize other performance bottlenecks. This paper discusses different instruction hints available on modern processor architectures and shows the potential performance impact on many benchmark programs. Some hints can be effectively selected at compile time with profile feedback. However, since the same program executable can behave differently on various inputs and performance bottlenecks may change on different micro-architectures, significant performance opportunities can be exploited by selecting instruction hints dynamically.


Data Cache Cache Line Normalize Execution Time Performance Bottleneck Memory Instruction 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Rao Fu
    • 1
  • Jiwei Lu
    • 2
  • Antonia Zhai
    • 1
  • Wei-Chung Hsu
    • 1
  1. 1.Department of Computer Science and EngineeringUniversity of Minnesota 
  2. 2.Scalable Systems GroupSun Microsystems Inc. 

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