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Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining

  • Jinhui Xu
  • Guiming Wu
  • Yong Dou
  • Yazhuo Dong
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4186)

Abstract

This paper introduces LEAP(Loop Engine on Array Processor), a novel coarse-grained reconfigurable architecture which accelerates applications through Loop Self-Pipelining (LSP) technique. The LSP can provide effective execution mode for application pipelining. By mapping and distributing the expression statements of high level programming languages onto processing elements array, the LEAP can step the loop iteration automatically. The LEAP architecture has no centralized control, no centralized multi-port registers and no centralized data memory. The LEAP has the ability to exploit loop-level, instruction-level, and task-level parallelism, and it is suitable choice for stream-based application domains, such as multimedia, DSP and graphics application.

Keywords

Data Memory Array Processor Execution Mode High Level Programming Language Interface Controller 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Jinhui Xu
    • 1
  • Guiming Wu
    • 1
  • Yong Dou
    • 1
  • Yazhuo Dong
    • 1
  1. 1.School of Computer ScienceNational University of Defense TechnologyChang Sha, Hu NanP.R. of China

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