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A Self-reconfigurable System-on-Chip Architecture for Satellite On-Board Computer Maintenance

  • Xiaofeng Wu
  • Tanya Vladimirova
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4186)

Abstract

New trends in the space industry, e.g. the development of wireless networked constellations using miniaturized satellites, have generated a pressing need for condition-based maintenance, self-repair and upgrade capabilities on-board satellites. This can be achieved by using reconfigurable hardware technologies, such as high-density Field Programmable Gate Arrays, implementing an entire on-board computer on a single chip. In this paper we present a system-on-chip architecture for on-board partial run-time reconfiguration to enable system-level functional changes on-board satellites ensuring correct operation, longer life and higher quality of service.

Keywords

Peripheral Device Onboard Computer Single Event Upset Partial Reconfiguration Intellectual Property Core 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Xiaofeng Wu
    • 1
  • Tanya Vladimirova
    • 1
  1. 1.Surrey Space Centre, Department of Electronic EngineeringUniversity of SurreyGuildfordUK

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