Acceleration Techniques for Chip-Multiprocessor Simulator Debug
By exploring thread-level parallelism, chip multiprocessor(CMP) can dramatically improve the performance of server and commercial applications. However, complex CMP chip architecture made debugging work time-consuming and rather hard. In this paper, based on the experience of debugging CMP simulator ThumpCMP, we present a set of acceleration techniques, including automatic cache-coherence check, fast error location, and workload rerun times reducing technique. The set of techniques have been demonstrated to be able to make CMP chip debugging work much easier and much faster.
KeywordsProcessor Core Acceleration Technique Cache Coherence Function Calling Virtual Address
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