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Design of a Reconfigurable Cryptographic Engine

  • Kang Sun
  • Lingdi Ping
  • Jiebing Wang
  • Zugen Liu
  • Xuezeng Pan
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4186)

Abstract

Cryptographic algorithms are usually compute-intensive and more efficiently implemented in hardware than in software. By taking advantage of FPGA technology, some work offers high performance and flexible solutions for cryptographic algorithms. But FPGAs still have some drawbacks. To overcome inherent shortages of FPGA, a novel asynchronous reconfigurable cryptographic engine (ARCEN) is introduced. In this architecture, reconfigurable cryptographic array is the kernel. It routes signals asynchronously between adjacent cells through Neighbor-to-Neighbor wires with 4-phase handshaking protocol. Computation circuit for reconfigurable cell is developed with modified DSDCVS logic. Experiment results show that the architecture has a better performance than FPGA.

Keywords

Cryptographic Algorithm Logic Cell Hash Family Operation Circuit Asynchronous Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Kang Sun
    • 1
  • Lingdi Ping
    • 1
  • Jiebing Wang
    • 1
  • Zugen Liu
    • 1
  • Xuezeng Pan
    • 1
  1. 1.College of Computer Science and TechnologyZhejiang UniversityHangzhouChina

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