Abstract
As technology scales down, the leakage energy accounts for more portion of total energy in a cache. Applying the Dynamic Voltage Scaling(DVS) to a cache, which is called a drowsy cache, is known as one of the most efficient techniques for reducing leakage energy in a cache. However, it increases the Soft Error Rate(SER) and many researchers began to doubt the reliability of a drowsy cache. In this paper, we show that the instruction cache(I-cache) can adopt the DVS without reliability problems for several reasons. First, an I-cache always stores read-only data, rarely incurring unrecoverable errors. In the I-cache, the soft error can be recovered by re-fetching from the lower level memory. Second, the effect of soft errors on performance is negligible, because the SER is extremely low. Additional, considerable percentage of soft errors do not harm the performance. In this paper, the evaluation results show that the drowsy I-cache rarely increases unrecoverable errors and negligibly degrades the performance.
This work was supported by the Brain Korea 21 Project.
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References
Degalahal, V., Li, L., Vijaykrishnan, N., Kandemir, M.T., Irwin, M.J.: Soft errors issues in low-power caches. In: VLSI, pp. 1157–1166 (2005)
Nguyen, H.T., Yagil, Y., Seifert, N., Reitsma, M.: Chip-level soft error estimation method. IEEE Transaction on Device and Materials Reliability, 365–381 (2005)
Hazucha, P., Svensson, C.: Impact of cmos technology scaling on the atmospheric neutron soft error rate. IEEE Transcation on Nuclear Science, 2586–2594 (2000)
Baumann, R.: Soft errors in advanced computer systems. IEEE Design and Test of Computers, 258–266 (2005)
Slayman, C.W.: Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations. IEEE Trans. on Device and Materials Reliability 5, 397–404 (2005)
Kim, N.S., Flautner, K., Blaauw, D., Mudge, T.N.: Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. In: MICRO, pp. 219–230 (2002)
Chen, C.L., Hsiao, M.Y.: Error-correcting codes for semiconductor memory applications: A state-of-the-art review. IBM Journal of Research and Development 28(2), 124–134 (1984)
Burger, D., Austin, T.M., Bennett, S.: Evaluating future microprocessors: the simplescalar tool set. Technical Report TR-1308, Univ. of Wisconsin-Madison Computer Sciences Dept. (1997)
SPEC: (SPEC CPU2000 Benchmarks), http://www.specbench.org
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Shin, S.H., Chung, S.W., Jhon, C.S. (2006). On the Reliability of Drowsy Instruction Caches. In: Jesshope, C., Egan, C. (eds) Advances in Computer Systems Architecture. ACSAC 2006. Lecture Notes in Computer Science, vol 4186. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11859802_42
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DOI: https://doi.org/10.1007/11859802_42
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