The Algorithm and Circuit Design of a 400MHz 16-Bit Hybrid Multiplier

  • Li Zhentao
  • Chen Shuming
  • Li Zhaoliang
  • Lei Conghua
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4186)


In this paper we present the algorithm of a 16-bit hybrid multiplier, which can work in two modes. In normal mode, it performs a 16-bit multi-plication. In SIMD mode, it performs two parallel 8-bit multiplications. The proposed algorithm is based on the raix-4 modified Booth’s algorithm. Our algorithm generates ten partial products and a modifier, which is five less than the other algorithms. We can get one 32-bit product or two 16-bit products by directly accumulating the ten partial products and the modifier, easing the design of the tree structures for compressing the partial products and the final adder. The proposed algorithm is adopted by YHFT-DSP/800, a high perfor-mance fixed-point DSP. The multiplier was full custom designed in 0.18um CMOS technology. We also designed a test chip. The test results show the multiplier works well at 400MHz in normal mode, 480MHz in SIMD mode. The simulated power is 35.8 mW at 400MHz, and 42.5 mW at 480MHz.


Digital Signal Processor Partial Product Test Chip SIMD Instruction Final Adder 
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  1. 1.
    DSPs Adapt to New Challenges. A White Paper by Berkeley Design Technology, Inc. (2003)Google Scholar
  2. 2.
    Michael, K., et al.: MMXTM Microarchitecture of Pentium® Processors With MMX Technology and Pentium®II Microprocessors. Intel Technology Journal, Q3 1997 (1997)Google Scholar
  3. 3.
    Magnus, S., et al.: An Efficient Twin-Precision Multiplier. In: Proc. of the IEEE 22nd International Conference on Computer Design (ICCD 2004), San Jose, California (2004)Google Scholar
  4. 4.
    Bewick, G.W.: Fast Multiplications: Algorithms and Imlementation. PhD thesis, Stanford University (1994)Google Scholar
  5. 5.
    Chen, S., Li, Z., et al.: Research and Development of High Performance YHFT Digital Signal Processor. Journal of Computer Research and Development 43 (2006)Google Scholar
  6. 6.
    Li, Z., Li, Z., Xing, Z.: The Full Custom Design of a 16-Bit Multiplier. In: NCCET 2005, Jinan (2005)Google Scholar
  7. 7.
    Knowles, S.: A family of adders. In: The15th IEEE Symposium on Computer Arithmetic (2001)Google Scholar
  8. 8.
    Kuo, Q.-W., et al.: Substrate-Bias Optimized 0.18um 2.5GHz 32-bit Adder with Post-Manufacture Tunable Clock. In: The 2005 International Symposium on VLSI Technology, Systems, and Applications (2005 VLSI-TSA), Hsinchu, Taiwan (2005)Google Scholar
  9. 9.
    Lei, C., Li, Z., Li, S.: The Circuit Optimization of a 32-Bit static Adder. In: NCCET 2005, Jinan (2005)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Li Zhentao
    • 1
  • Chen Shuming
    • 1
  • Li Zhaoliang
    • 1
  • Lei Conghua
    • 1
  1. 1.School of Computer Science and TechnologyNational University of Defense TechnologyChangshaChina

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