Issues and Support for Dynamic Register Allocation

  • Abhinav Das
  • Rao Fu
  • Antonia Zhai
  • Wei-Chung Hsu
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4186)


Post-link and dynamic optimizations have become important to achieve program performance. A major challenge in post-link and dynamic optimizations is the acquisition of registers for inserting optimization code in the main program. It is difficult to achieve both correctness and transparency when software-only schemes for acquiring registers are used, as described in [1]. We propose an architecture feature that builds upon existing hardware for stacked register allocation on the Itanium processor. The hardware impact of this feature is minimal, while simultaneously allowing post-link and dynamic optimization systems to obtain registers for optimization in a “safe” manner, thus preserving the transparency and improving the performance of these systems.


Dynamic Optimization Architecture Feature Regular Mode Register Allocation Register Window 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Abhinav Das
    • 1
  • Rao Fu
    • 1
  • Antonia Zhai
    • 1
  • Wei-Chung Hsu
    • 1
  1. 1.Department of Computer ScienceUniversity of Minnesota 

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