Abstract
This paper describes a control system processor architecture based on ΔΣ modulation (ΔΣ-CSP). The ΔΣ-CSP uses 1-bit processing which is a new concept in digital control to remove multi-bit multiplications. A simple conditional-negate-and-add (CNA) unit is proposed for most operations of control laws. For this reason, the targeted processor is small and very fast, making it ideal for embedded real-time control applications. The ΔΣ-CSP has been implemented as a VLSI hard macro in a high-performance 0.13μm silicon process. Results show that it compares very favorably to other digital processors in terms of area and clock frequency.
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© 2006 Springer-Verlag Berlin Heidelberg
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Wu, X., Chouliaras, V., Nunez-Yanez, J., Goodall, R., Vladimirova, T. (2006). A Novel Processor Architecture for Real-Time Control. In: Jesshope, C., Egan, C. (eds) Advances in Computer Systems Architecture. ACSAC 2006. Lecture Notes in Computer Science, vol 4186. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11859802_22
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DOI: https://doi.org/10.1007/11859802_22
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40056-1
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