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A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster

  • Arata Shinozaki
  • Masatoshi Shima
  • Minyi Guo
  • Mitsunori Kubo
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4186)

Abstract

In the ubiquitous era, it is necessary to research on the architectures of multiprocessor system with high performance and low power consumption. A processor simulator developed in high level language is useful because of its easily changeable system architecture which includes application specific instruction sets and functions. However, there is a problem in processing speed that both PCs and workstations provide insufficient performance for the simulation of a multiprocessor system. In this research, a simulator for a multiprocessor system based on the multi-way cluster was developed. In the developed simulator system, one processor model consists of an instruction set simulator (ISS) process and several inter-processor communication processes. In order to get the maximization of the simulation performance, each processor model is assigned to the specific CPU on the multi-way cluster. Also, each inter-processor communication process is implemented using MPI library, which can minimize the CPU resource usage in a communication waiting state. The evaluation results of the processing and communication performance using a distributed application program such as JPEG encoding show that each ISS process in the developed simulator system consumes approximately 100% CPU resources for keeping enough inter-processor communication performance. This result means that the performance increases in proportion to the number of integrated CPUs on the cluster.

Keywords

Processing Module Processing Element Simulator System Multiprocessor System Communication Module 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Matsuzawa, A.: Issues of Current LSI Technology and the Future Technology Direction. IEICE Transactions J87-C (11), 802–809 (2004)Google Scholar
  2. 2.
    Pham, D., et al.: The Design and Implementation of a First-Generation CELL Processor – A Multi-Core SoC. In: ICICDT 2005, pp. 49–52 (2005)Google Scholar
  3. 3.
    Intel PentiumD Processor (March 2006), http://www.intel.com/products/processor/index.htm
  4. 4.
    Imafuku, S., Ohno, K., Nakashima, H.: Reference filtering for distributed simulation of shared memory multi-processor. In: Proc. 34th Annual Simulation Symposium, pp. 219–226 (May 2001)Google Scholar
  5. 5.
    Mukherjee, S., Reinhardt, S., Falsafi, B., Litzkow, M., Huss-Lederman, S., Hill, M., Larus, J., Wood, D.: Wisconsin Wind Tunnel II: A fast and portable parallel architecture simulator. In: Proc. Workshop on Performance Analysis and Its Impact on Design (June 1997)Google Scholar
  6. 6.
    Rosenblum, M., Herrod, S., Witchel, E., Gupta, A.: Complete computer system simulation: The SimOS approach. IEEE Parallel & Distributed Technology 3(4), 34–43 (1995)CrossRefGoogle Scholar
  7. 7.
    Veenstra, J., Fowler, R.: Mint: A front end for efficient simulation of shared-memory multi-processor. In: Proc. MASCOTS 1994, pp. 201–207 (1994)Google Scholar
  8. 8.
    Cmelik, R., Keppel, D.: Shade: A fast instruction set simulator for execution profiling. In: Proc. of 1994 ACM SIGMETTRICS Conference on Measurement and Modeling of computer systems, Philadelphia (1996)Google Scholar
  9. 9.
    Shima, M., Shinozaki, A., Sato, T.: Cycle-Accurate Processor Modeling Written in Java Language. IEICE CPSY2002-53, pp. 13–18 (2002)Google Scholar
  10. 10.
    Shima, M., Shinozaki, A., Ohta, S., Ito, K.: Cycle-Accurate System Modeling in Java. IEICE VLD2002-146, pp. 1–6 (2003)Google Scholar
  11. 11.
    Grotker, T., Liao, S., Martin, G., Swan, S.: System Design with SystemC. Kluwer Academic Publishers, Dordrecht (2003)Google Scholar
  12. 12.
    SystemC Community (March 2004), http://www.systemc.org/
  13. 13.
  14. 14.
    HyperTransport Consortium (Current March, 2006), http://www.hypertransport.org/
  15. 15.
    Pacheco, P.: Parallel Programming with MPI. Morgan Kaufmann Publishers, San Francisco (1997)MATHGoogle Scholar
  16. 16.
    SUSE Linux (Current March, 2006), http://www.novell.com/linux/
  17. 17.
    Kane, G., Heinrich, J.: MIPS RISC ARCHITECTURE. Prentice Hall PTR, Englewood Cliffs (1992)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Arata Shinozaki
    • 1
  • Masatoshi Shima
    • 1
  • Minyi Guo
    • 2
  • Mitsunori Kubo
    • 1
  1. 1.Future Creation Lab., Olympus Corp.Shinjuku-ku, TokyoJapan
  2. 2.School of Computer Science and Eng.University of AizuAizu-Wakamatsu, FukushimaJapan

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