An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit

  • Farhad Mehdipour
  • Hamid Noori
  • Morteza Saheb Zamani
  • Kazuaki Murakami
  • Mehdi Sedighi
  • Koji Inoue
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4186)


Extensible processors allow customization for an application by extending the core instruction set architecture. Extracting appropriate custom instructions is an important phase for implementing an application on an extensible processor with a reconfigurable functional unit. Custom instructions (CIs) usually are extracted from critical portions of applications. This paper presents approaches for CI generation with respect to the RFU constraints to improve speedup of the extensible processor. First, our proposed RFU architecture for an adaptive dynamic extensible processor called AMBER is described. Then, an integrated temporal partitioning and mapping framework is presented to partition and map the CIs on the RFU. In this framework, a mapping aware temporal partitioning algorithm is used to generate CIs which are mappable on the RFU. Temporal partitioning iterates and modifies partitions incrementally to generate CIs. In addition, a mapping algorithm is presented which supports CIs with critical path length more than the RFU depth.


Critical Path Integrate Framework Mapping Framework Custom Instruction Data Flow Graph 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Arnold, M., Corporaal, H.: Designing domain-specific processors. In: Proceedings of the Design, Automation and Test in Europe Conf., pp. 61–66 (2001)Google Scholar
  2. 2.
    Atasu, K., Pozzi, L., Lenne, P.: Automatic application-specific instruction-set extensions under microarchitectural constraints. In: 40th Design Automation Conference (2003)Google Scholar
  3. 3.
    Bobda, C.: Synthesis of dataflow graphs for reconfigurable systems using temporal partitioning and temporal placement, Ph.D thesis, Faculty of Computer Science, Electrical Engineering and Mathematics, University of Paderborn (2003)Google Scholar
  4. 4.
    Clark, N., Kudlur, M., Park, H., Mahlke, S., Flautner, K.: Application-specific processing on a general-purpose core via transparent instruction set customization. In: Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture (2004)Google Scholar
  5. 5.
    Halfhill, T.R.: MIPS embraces configurable technology, Microprocessor Report (March 3, 2003)Google Scholar
  6. 6.
    Karthikeya, M., Gajjala, P., Dinesh, B.: Temporal partitioning and scheduling data flow graphs for reconfigurable computer. IEEE Transactions on Computers 48(6), 579–590 (1999)CrossRefGoogle Scholar
  7. 7.
    Kastner, R., Kaplan, A., Ogrenci Memik, S., Bozorgzadeh, E.: Instruction generation for hybrid reconfigurable systems. ACM TODAES 7(4), 605–627 (2002)CrossRefGoogle Scholar
  8. 8.
    Lee, C., Potkonjak, M., Mangione-Smith, W.H.: MediaBench: A tool for evaluating and synthesizing multimedia and communications systems. In: Proceedings of the 30-th Annual Intl. Symp. On Microarchitecture, pp. 330–335 (1997)Google Scholar
  9. 9.
    Mehdipour, F., Saheb Zamani, M., Sedighi, M.: An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing system. International Journal of Microprocessors and Microsystems 30(1), 52–62 (2006)CrossRefGoogle Scholar
  10. 10.
    Micheli, G.D.: Synthesis and optimization of digital circuits. McGraw-Hill, New York (1994)Google Scholar
  11. 11.
    Noori, H., Murakami, K., Inoue, K.: General overview of an adaptive dynamic extensible processor architecture. In: Workshop on Introspective Architecture (WISA 2006) (2006)Google Scholar
  12. 12.
    Ouaiss, I., Govindarajan, S., Srinivasan, V., Kaul, M., Vemuri, R.: An integrated partitioning and synthesis system for dynamically reconfigurable multi-FPGA architectures. In: Proceedings of the Reconfigurable Architecture Workshop, pp. 31–36 (1998)Google Scholar
  13. 13.
    Razdan, R., Smith, M.D.: A high-performance microarchitecture with hardware-programmable functional units. In: Proceedings of the 27th Annual International Symposium on Microarchitecture, pp. 172–180 (1994)Google Scholar
  14. 14.
    Spillane, J., Owen, H.: Temporal partitioning for partially reconfigurable field programmable gate arrays. In: IPPS/SPDP Workshops, pp. 37–42 (1998)Google Scholar
  15. 15.
    Tanougast, C., Berviller, Y., Brunet, P., Weber, S., Rabah, H.: Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system. International Journal of Microprocessors and Microsystems 27, 115–130 (2003)CrossRefGoogle Scholar
  16. 16.
    Writhlin, M., Hutchings, B.: A dynamic instruction set computer. In: Proceeding IEEE Symposium on Field Programmable Custom Computing Machines, pp. 99–107. IEEE Computer Society Press, Los Alamitos (1995)Google Scholar
  17. 17.
    Ye, Z.A., et al.: Chimaera: A high-performance architecture with tightly-coupled reconfigurable functional unit. In: Proceeding of 27th ISCA, pp. 225–235 (2000)Google Scholar
  18. 18.
    Yu, P., Mitra, T.: Characterizing embedded applications for instruction-set extensible processors. In: Proceedings of Design and Automation Conference, pp. 723–728 (2004)Google Scholar
  19. 19.
  20. 20.

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Farhad Mehdipour
    • 1
  • Hamid Noori
    • 2
  • Morteza Saheb Zamani
    • 1
  • Kazuaki Murakami
    • 2
  • Mehdi Sedighi
    • 1
  • Koji Inoue
    • 2
  1. 1.Computer and IT Engineering DepartmentAmirkabir University of TechnologyTehranIran
  2. 2.Department of Informatics, Graduate School of Information Science and Electrical EngineeringKyushu UniversityJapan

Personalised recommendations