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A High Performance Heterogeneous Architecture and Its Optimization Design

  • Jianjun Guo
  • Kui Dai
  • Zhiying Wang
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4208)

Abstract

The widely adoption of media processing applications provides great challenges to high performance embedded processor design. This paper studies a Data Parallel Coprocessor architecture based on SDTA and architecture de-cisions are made for the best performance/cost ratio. Experimental results on a prototype show that SDTA has high performance to run many embedded media processing applications. The simplicity and flexibility of SDTA encourages for further development for its reconfigurable functionality.

Keywords

Data Parallel SDTA ASIP 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Jianjun Guo
    • 1
  • Kui Dai
    • 1
  • Zhiying Wang
    • 1
  1. 1.School of ComputerNational University of Defense TechnologyChangsha, HunanChina

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