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Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and Performance

  • A. G. Silva-Filho
  • F. R. Cordeiro
  • R. E. Sant’Anna
  • M. E. Lima
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)

Abstract

In this work is presented an automated method for adjusting two-level cache memory hierarchy in order to reduce energy consumption in embedded applications. The proposed heuristic, TECH-CYCLES (Two-level Cache Exploration Heuristicconsidering CYCLES), consists of making a small search in the space of configurations of the two-level cache hierarchy, analyzing the impact of each parameter in terms of energy and number of cycles spent for a given application. Experiments show an average reduction of about 41% in the energy consumption by using our heuristic when compared with the existing heuristic (TCaT), also for two-level caches. Besides the energy improvement, this method also reduces the number of cycles needed to execute a given application by about 25%. In order to validate the proposed heuristic, twelve benchmarks from the MiBench suite have been used.

Keywords

Cache Size Data Cache Instruction Cache Cache Hierarchy Cache Associativity 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • A. G. Silva-Filho
    • 1
  • F. R. Cordeiro
    • 1
  • R. E. Sant’Anna
    • 2
  • M. E. Lima
    • 2
  1. 1.Department of Computational SystemsUniversity of Pernambuco (UPE)RecifeBrazil
  2. 2.Informatics CenterFederal University of Pernambuco (UFPE)RecifeBrazil

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