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Top Verification of Low Power System with “Checkerboard” Approach

  • Jean Oudinot
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)

Abstract

Low power management is a critical design front for complex wireless systems. Not only different natures of the blocks required different power supplies (1.5V, 2.5V). Blocks are switched on and off sequentially during the duty to save power. A simple connection error can damage or destroy a block. Top level verification of such a complexity is required to guaranty the quality and the robustness of the final product.

Keywords

Critical Path Functional Performance Active Block Memory Structure Preparation Phase 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Jean Oudinot
    • 1
  1. 1.Mentor Graphics 

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