Abstract
Low power management is a critical design front for complex wireless systems. Not only different natures of the blocks required different power supplies (1.5V, 2.5V). Blocks are switched on and off sequentially during the duty to save power. A simple connection error can damage or destroy a block. Top level verification of such a complexity is required to guaranty the quality and the robustness of the final product.
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© 2006 Springer-Verlag Berlin Heidelberg
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Oudinot, J. (2006). Top Verification of Low Power System with “Checkerboard” Approach. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_69
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DOI: https://doi.org/10.1007/11847083_69
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
Online ISBN: 978-3-540-39097-8
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