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A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits

  • Felipe Machado
  • Teresa Riesgo
  • Yago Torroja
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)

Abstract

The analysis of circuit switching activity is a fundamental step towards dynamic power estimation of CMOS digital circuits. In this paper, a probabilistic method for switching activity estimation of VHDL-RTL combinatorial designs is presented. Switching activity estimation is performed through the propagation of input signals probabilities and switching activities by means of BDDs (Binary Decision Diagrams). In order to avoid the BDD memory explosion of large circuits, an automatic circuit partition is performed taking advantage of the specific characteristics of some VHDL statements that permit the circuit division in exclusive regions. In addition, a reduced representation of switching activity BDDs is proposed. The method is implemented in a CAD tool, which, besides the signal probabilities and switching activities, offers abundant information and means for circuit exploration.

Keywords

Boolean Function Signal Probability Switching Activity Binary Decision Diagram Node Arrangement 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Felipe Machado
    • 1
  • Teresa Riesgo
    • 1
  • Yago Torroja
    • 1
  1. 1.División de Ingeniería ElectrónicaUniversidad Politécnica de Madrid, E.T.S.I. IndustrialesMadridSpain

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