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Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks

  • Alin Razafindraibe
  • Michel Robert
  • Philippe Maurine
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)

Abstract

Based on a first order model of the switching current flowing in CMOS cell, an investigation of the robustness against DPA of dual-rail logic is carried out. The result of this investigation, performed on 130nm process, is a formal identification of the design range in which dual-rail logic can be considered as robust.

Keywords

Cmos Inverter Differential Power Analysis Validity Domain Asynchronous Circuit Design Range 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Kocher, P.C., Jaffe, J., Jun, B.: Differential Power Analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999)Google Scholar
  2. 2.
    Suzuki, D., et al.: Random Switching Logic: A Countermeasure against DPA based on Transition Probability, Cryptology ePrint Archive, 2004/346, http://eprint.iacr.org/complete/
  3. 3.
    Sokolov, D., et al.: Design and Analysis of Dual-Rail Circuits for Security Applications. IEEE Trans. on Computers 54(4), 449–460 (2005)CrossRefGoogle Scholar
  4. 4.
    Guilley, S., et al.: CMOS structures suitable for secured hardware. In: Design, Automation and Test in Europe Conference and ExpositionGoogle Scholar
  5. 5.
    Fournier, J.J.A., Moore, S., Li, H., Mullins, R., Taylor, G.: Security evaluation of asynchronous circuits. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 137–151. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  6. 6.
    Bouesse, G.F., et al.: DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. Design, Automation and Test in Europe 1, 424–429 (2005)CrossRefGoogle Scholar
  7. 7.
    Razafindraibe, A., et al.: Secured structures for secured asynchronous QDI circuits. In: XIX Conference on Design of Circuits and Integrated Systems, November 24-26 (2004)Google Scholar
  8. 8.
    Tiri, K., Verbauwhede, I.: Securing encryption algorithms against DPA at the logic level: Next generation smart card technology. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 125–136. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  9. 9.
    Tiri, K., et al.: A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs. In: Design, Automation and Test in Europe (DATE 2005), vol. 3, pp. 58–63 (2005)Google Scholar
  10. 10.
    Mace, F., et al.: A dynamic current mode logic to counteract power analysis attacks. In: DCIS 2004 (2004)Google Scholar
  11. 11.
    Maurine, P., et al.: Transition time modeling in deep submicron CMOS. IEEE Trans. on CAD 21(11), 1352–1363 (2002)Google Scholar
  12. 12.
    Jeppson, K.O.: Modeling the Influence of the Transistor Gain Ratio and the Input-to-Output Coupling Capacitance on the CMOS Inverter Delay. IEEE JSSC 29, 646–654 (1994)Google Scholar
  13. 13.
    Tsividis, T.: Operation and Modeling of the Mos Transistor. Oxford University Press, Oxford (1999)Google Scholar
  14. 14.
    Sakurai, T., et al.: Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE J. Solid-State Circuits 25, 584–594 (1990)CrossRefGoogle Scholar
  15. 15.
    Sparso, J., et al.: Principles of Asynchronous Circuit Design: A Systems Perspective. Kluwer Academic Publishers, DordrechtGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Alin Razafindraibe
    • 1
  • Michel Robert
    • 1
  • Philippe Maurine
    • 1
  1. 1.Microelectronics DepartmentLIRMMMontpellierFrance

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